公开(公告)号：US11251070B2

公开(公告)日：2022-02-15

申请号：US17016537

申请日：2020-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiseok Hong ,  Chan-Sic Yoon ,  Ilyoung Moon ,  Jemin Park ,  Kiseok Lee ,  Jung-Hoon Han

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A method of fabricating a semiconductor device includes providing a substrate, and forming an interlayered insulating layer on the substrate. The method includes forming a preliminary via hole in the interlayered insulating layer. The method includes forming a passivation spacer on an inner side surface of the preliminary via hole. The method includes forming a via hole using the passivation spacer as an etch mask. The method includes forming a conductive via in the via hole. The passivation spacer includes an insulating material different from an insulating material included in the interlayered insulating layer.

公开(公告)号：US20220028859A1

公开(公告)日：2022-01-27

申请号：US17191308

申请日：2021-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho HONG ,  Kyunghwan Lee ,  Hyuncheol Kim ,  Huijung Kim ,  Hyunmog Park ,  Kiseok Lee ,  Minhee Cho

IPC: H01L27/108 ,  G11C5/06 ,  H01L29/24

Abstract: A memory device is provided. The memory device includes: a substrate; a memory unit provided on the substrate; a channel provided on the memory unit; a word line surrounded by the channel and extending in a first horizontal direction; a gate insulating layer interposed between the channel and the word line; and a bit line contacting an upper end of the channel and extending in a second horizontal direction that crosses the first horizontal direction.

公开(公告)号：US20210398569A1

公开(公告)日：2021-12-23

申请号：US17168952

申请日：2021-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiseok Hong ,  Sangho Lee ,  Seoryong Park ,  Jiyoung Ahn ,  Kiseok Lee ,  Kiseok Lee ,  Yoonyoung Choi ,  Seunguk Han

IPC: G11C5/06 ,  H01L27/108

Abstract: An integrated circuit device includes: a substrate including a plurality of active regions; a bit line extending on the substrate in a horizontal direction; a direct contact connected between a first active region selected among the plurality of active regions and the bit line; an inner oxide layer contacting a sidewall of the direct contact; and a carbon-containing oxide layer nonlinearly extending on a sidewall of the bit line in a vertical direction, the carbon-containing oxide layer contacting the sidewall of the bit line.

公开(公告)号：US20210351184A1

公开(公告)日：2021-11-11

申请号：US17384347

申请日：2021-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyosub Kim ,  Keunnam Kim ,  Dongoh Kim ,  Bongsoo Kim ,  Euna Kim ,  Chansic Yoon ,  Kiseok Lee ,  Hyeonok Jung ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

公开(公告)号：US11079895B2

公开(公告)日：2021-08-03

申请号：US14883940

申请日：2015-10-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohy Hong ,  Kyungwhoon Cheun ,  Jisung Oh ,  Kiseok Lee ,  Dongjoo Choi

IPC: G06F3/0481 ,  G06F3/0484 ,  G06F3/0488

Abstract: The present disclosure relates to a sensor network, Machine Type Communication (MTC), Machine-to-Machine (M2M) communication, and technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the above technologies, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. A method of providing a user interface (UI) by an electronic device is provided. The method includes displaying a control UI, receiving a first drag input via the displayed control UI, and, when a direction of the first drag input corresponds to a first direction, displaying a cursor UI at a preset location. According to an embodiment of the present disclosure, a UI through which an electronic device can easily receive a user input may be provided.

公开(公告)号：US10937833B2

公开(公告)日：2021-03-02

申请号：US16455791

申请日：2019-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung Kim ,  Kiseok Lee ,  Keunnam Kim ,  Yoosang Hwang

IPC: H01L47/00 ,  H01L27/24 ,  H01L45/00 ,  H01L43/08

Abstract: Disclosed is a variable resistance memory device including a first conductive line extending in a first direction parallel to a top surface of the substrate, memory cells spaced apart from each other in the first direction on a side of the first conductive line and connected to the first conductive line, and second conductive lines respectively connected to the memory cells. Each second conductive line is spaced apart in a second direction from the first conductive line. The second direction is parallel to the top surface of the substrate and intersects the first direction. The second conductive lines extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction. Each memory cell includes a variable resistance element and a select element that are positioned at a same level horizontally arranged in the second direction.

公开(公告)号：US10910378B2

公开(公告)日：2021-02-02

申请号：US16268748

申请日：2019-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Bong-Soo Kim ,  Jiyoung Kim ,  Hui-Jung Kim ,  Seokhan Park ,  Hunkook Lee ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/08 ,  H01L29/165 ,  H01L29/10 ,  H01L23/522 ,  H01L49/02

Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.

公开(公告)号：US10784272B2

公开(公告)日：2020-09-22

申请号：US16027887

申请日：2018-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Junsoo Kim ,  Hui-Jung Kim ,  Bong-Soo Kim ,  Satoru Yamada ,  Kyupil Lee ,  Sunghee Han ,  HyeongSun Hong ,  Yoosang Hwang

IPC: H01L27/11556 ,  H01L23/532 ,  G11C7/18 ,  H01L49/02 ,  G11C8/14 ,  H01L27/11524 ,  G11C11/404 ,  G11C11/4097

Abstract: A semiconductor memory device comprises a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also comprises a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer comprises semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

公开(公告)号：US10468414B2

公开(公告)日：2019-11-05

申请号：US16115693

申请日：2018-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung Kim ,  Kiseok Lee ,  Junsoo Kim ,  Sunghee Han ,  Bong-Soo Kim ,  Yoosang Hwang

IPC: H01L27/11578 ,  H01L27/108 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/45 ,  H01L23/528 ,  H01L29/792

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate and a stack including a plurality of layers on the substrate. Each of the plurality of layers includes semiconductor patterns and a first conductive line that is connected to at least one of the semiconductor patterns. A second conductive line and a third conductive line penetrate the stack. The semiconductor patterns include a first semiconductor pattern and a second semiconductor pattern that are adjacent and spaced apart from each other in a first layer among the plurality of layers. The third conductive line is between, and connected in common to, the first and second semiconductor patterns.

公开(公告)号：US10461153B2

公开(公告)日：2019-10-29

申请号：US15890707

申请日：2018-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Myeong-Dong Lee ,  Hui-Jung Kim ,  Dongoh Kim ,  Bong-Soo Kim ,  Seokhan Park ,  Woosong Ahn ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L29/06 ,  H01L27/108 ,  H01L23/535 ,  H01L23/528

Abstract: A semiconductor memory device includes a substrate including active regions, word lines in the substrate and each extending in a first direction parallel to an upper surface of the substrate, bit line structures connected to the active regions, respectively, and each extending in a second direction crossing the first direction, and spacer structures on sidewalls of respective ones of the bit line structures. Each of the spacer structures includes a first spacer, a second spacer, and a third spacer. The second spacer is disposed between the first spacer and the third spacer and includes a void defined by an inner surface of the second spacer. A height of the second spacer is greater than a height of the void.