公开(公告)号：US20240363734A1

公开(公告)日：2024-10-31

申请号：US18770088

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ying Hsin Lu ,  Ling-Sung Wang

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/28088 ,  H01L21/76877 ,  H01L21/82345 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481

Abstract: A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.

公开(公告)号：US20240363425A1

公开(公告)日：2024-10-31

申请号：US18769679

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Chung Chiu ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3065 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/823462 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66795 ,  H01L27/088

Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.

公开(公告)号：US20240347465A1

公开(公告)日：2024-10-17

申请号：US18753766

申请日：2024-06-25

Applicant: Intel Corporation

Inventor： Atul MADHAVAN ,  Nicholas J. KYBERT ,  Mohit K. HARAN ,  Hiten KOTHARI

IPC: H01L23/535 ,  H01L21/02 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/45 ,  H01L29/51

CPC classification number: H01L23/535 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/518 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/0276 ,  H01L21/31144 ,  H01L29/45

Abstract: Contact over active gate (COAG) structures with etch stop layers, and methods of fabricating contact over active gate (COAG) structures using etch stop layers, are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A first dielectric etch stop layer is directly on and continuous over the trench insulating layers and the gate insulating layers. A second dielectric etch stop layer is directly on and continuous over the first dielectric etch stop layer, the second dielectric etch stop layer distinct from the first dielectric etch stop layer. An interlayer dielectric material is on the second dielectric etch stop layer.

公开(公告)号：US20240347347A1

公开(公告)日：2024-10-17

申请号：US18749029

申请日：2024-06-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shahaji B. MORE ,  Chandrashekhar Prakash SAVANT

IPC: H01L21/3213 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L21/32139 ,  H01L21/28079 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0924

Abstract: A semiconductor device includes a substrate; first and second fin structures extending above the substrate; a metal layer on the first and second fin structures; an isolation structure extending through the metal layer between the first and second fin structures, the isolation structure being configured to electrically isolate a first portion of the metal layer on the first fin structure from a second portion of the metal layer on the second fin structure, and the isolation structure having substantially vertical sidewalls; and a passivation layer between at least an upper portion of the isolation structure and an adjacent portion of the metal layer, the passivation layer extending laterally into the metal layer.

公开(公告)号：US12113120B2

公开(公告)日：2024-10-08

申请号：US17813814

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ying Hsin Lu ,  Ling-Sung Wang

IPC: H01L29/08 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/28088 ,  H01L21/76877 ,  H01L21/82345 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481

Abstract: A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.

公开(公告)号：US12112983B2

公开(公告)日：2024-10-08

申请号：US17003616

申请日：2020-08-26

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： Timothy E. Boles ,  Wayne Mack Struble ,  Gabriel R. Cueva

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/532 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L21/76841 ,  H01L21/823437 ,  H01L23/53223 ,  H01L29/2003 ,  H01L29/42372

Abstract: An electrode structure for a device, such as a GaN or AlGaN device is described. In one example, a method to form the structure includes providing a substrate including gallium nitride material, forming an insulating layer over a surface of the substrate, forming an opening in the insulating layer to expose a surface region of the substrate, depositing a barrier metal layer over the insulating layer and onto the surface region of the substrate through the opening, and depositing a conducting metal layer over the barrier metal layer. In one case, the barrier metal layer includes a layer of tungsten nitride. The layer of tungsten nitride is deposited over the insulating layer and onto the surface region of the substrate using atomic layer deposition.

公开(公告)号：US20240322011A1

公开(公告)日：2024-09-26

申请号：US18737803

申请日：2024-06-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Yi PENG ,  Wen-Yuan CHEN ,  Wen-Hsing HSIEH ,  Yi-Ju HSU ,  Jon-Hsu HO ,  Song-Bor LEE ,  Bor-Zen TIEN

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/66545 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02203 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886

Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.

公开(公告)号：US12101091B2

公开(公告)日：2024-09-24

申请号：US18306469

申请日：2023-04-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Szu-Lin Liu ,  Jaw-Juinn Horng ,  Yi-Hsiang Wang ,  Wei-Lin Lai

IPC: H03K5/12 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/94 ,  H03K5/1252 ,  H03K19/0185

CPC classification number: H03K5/1252 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0629 ,  H01L29/94 ,  H03K19/018521

Abstract: A method includes fabricating a first transistor and a second transistor on a substrate and fabricating a first conducting line and a second conducting line in a first metal layer. The method also includes connecting a gate of the first transistor to the first conducting line and connecting a gate of the second transistor to the second conducting line. The first conducting line and the second conducting line are parallel and adjacent to each other in the first metal layer above the first transistor and the second transistor. The method still includes connecting a source and a drain of the first transistor to a third conducting line.

公开(公告)号：US12087857B2

公开(公告)日：2024-09-10

申请号：US17404114

申请日：2021-08-17

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Yukun Li ,  Tao Chen

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L21/26533 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/7834

Abstract: The application provides a method for manufacturing a semiconductor device. The method includes the following operations. A semiconductor substrate is provided, a plurality of separate trenches being formed in the semiconductor substrate. Plasma injection is performed to form a barrier layer between adjacent trenches A respective gate structure is formed in each of the plurality of trenches. A plurality of channel regions are formed in the semiconductor substrate, each of the plurality of trenches corresponding to a respective one of the plurality of channel regions. A source/drain region is formed between each of the plurality of trenches and the barrier layer, the source/drain region being electrically connected to the respective one of the plurality of channel regions, and a conductive type of the barrier layer is opposite to a conductive type of the source/drain region.

公开(公告)号：US20240290866A1

公开(公告)日：2024-08-29

申请号：US18540280

申请日：2023-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonhyuk HONG ,  Jongjin LEE ,  Taesun KIM ,  Myunghoon JUNG ,  Kang-ill SEO

IPC: H01L29/66 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5286 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A system and a method are disclosed for forming a bottle-neck shaped backside contact structure in a semiconductor device, wherein the bottle-neck shaped backside contact structure has a first side partially within the first source/drain structure, a second side contacting a backside power rail, and a liner extending from the first side to the backside power rail. The liner includes a first region comprised of either a Ta silicide liner or a Ti silicide liner, a second region comprised of a Ti/TiN liner and a third region comprised of either a Ta silicide liner or a Ti silicide liner. The backside contact structure includes a first portion having a positive slope and a second portion, adjacent to the first portion, having no slope.