公开(公告)号：US20240365561A1

公开(公告)日：2024-10-31

申请号：US18770108

申请日：2024-07-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tzu-Yu CHEN ,  Sheng-Hung SHIH ,  Fu-Chen CHANG ,  Kuo-Chi TU ,  Wen-Ting CHU

IPC: H10B53/30 ,  H01L21/02

CPC classification number: H10B53/30 ,  H01L21/0234 ,  H01L21/02356 ,  H01L28/60

Abstract: A semiconductor device includes a bottom electrode, a top electrode, a sidewall spacer, and a data storage element. The sidewall spacer is disposed aside the top electrode. The data storage element is located between the bottom electrode and the top electrode, and includes a ferroelectric material. The data storage element has a peripheral region which is disposed beneath the sidewall spacer and which has at least 60% of ferroelectric phase. A method for manufacturing the semiconductor device and a method for transforming a non-ferroelectric phase of a ferroelectric material to a ferroelectric phase are also disclosed.

公开(公告)号：US12110589B2

公开(公告)日：2024-10-08

申请号：US16631979

申请日：2018-08-01

Applicant: Applied Materials, Inc.

Inventor： Tatsuya E. Sato ,  Wei Liu ,  Li-Qun Xia

IPC: C23C16/455 ,  C23C16/40 ,  H01L21/02

CPC classification number: C23C16/45553 ,  C23C16/403 ,  C23C16/4554 ,  C23C16/45548 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/0234

Abstract: Methods comprising forming a metal oxide film by atomic layer deposition using water as an oxidant are described. The metal oxide film is exposed to a decoupled plasma comprising one or more of He, H2 or O2 to lower the wetch etch rate of the metal oxide film.

公开(公告)号：US12087572B2

公开(公告)日：2024-09-10

申请号：US17598830

申请日：2020-03-26

Applicant: Lam Research Corporation

Inventor： Bart J. van Schravendijk ,  Soumana Hamma ,  Kai-Lin Ou ,  Ming Li ,  Malay Milan Samantaray

IPC: H01L21/02 ,  H01L21/311 ,  H01L27/088 ,  H01L27/1157 ,  H10B43/20 ,  H10B43/35

CPC classification number: H01L21/0217 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/31111 ,  H01L27/088 ,  H10B43/20 ,  H10B43/35

Abstract: Disclosed are methods for the formation of silicon nitride (SiN) on only the horizontal surfaces of structures such as 3D NAND staircase. This allows for thicker landing pads for subsequently formed vias. In some embodiments, the methods involve deposition of a SiN layer over a staircase followed by a treatment to selectively densify the SiN layer on the horizontal surfaces with respect to the sidewall surfaces. A wet etch is then performed to remove SiN from the sidewall surfaces. The selective treatment results in significantly different wet etch rates (WERs) between the horizontal surfaces and the sidewalls.

公开(公告)号：US12080553B2

公开(公告)日：2024-09-03

申请号：US17353380

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Sung-En Lin ,  Chi On Chui

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/033 ,  H01L29/66

CPC classification number: H01L21/0338 ,  H01L21/02181 ,  H01L21/0234 ,  H01L21/02356 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/76805 ,  H01L21/76895 ,  H01L29/66795

Abstract: Structures and methods of forming semiconductor devices are presented in which a void-free core-shell hard mask is formed over a gate electrode. The void-free core-shell hard mask may be formed in some embodiments by forming a first liner layer over the gate electrode, forming a void-free material over the first liner layer, recessing the void-free material, and forming a second liner over the recessed void-free material.

公开(公告)号：US12057310B2

公开(公告)日：2024-08-06

申请号：US17501842

申请日：2021-10-14

Applicant: VERSUM MATERIALS US, LLC

Inventor： Manchao Xiao ,  Matthew R MacDonald

IPC: H01L21/02 ,  C07F7/10 ,  C23C16/34 ,  C23C16/40 ,  C23C16/455 ,  C23C16/56

CPC classification number: H01L21/02222 ,  C07F7/10 ,  C23C16/345 ,  C23C16/402 ,  C23C16/45553 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02277 ,  H01L21/0228 ,  H01L21/0234

Abstract: Described herein are functionalized cyclosilazane precursor compounds and compositions and methods comprising same to deposit a silicon-containing film such as, without limitation, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or carbon-doped silicon oxide via a thermal atomic layer deposition (ALD) or plasma enhanced atomic layer deposition (PEALD) process, or a combination thereof.

公开(公告)号：US12051746B2

公开(公告)日：2024-07-30

申请号：US17884388

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Liang Cheng ,  Ziwei Fang

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/033 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L29/7813 ,  H01L21/02172 ,  H01L21/022 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0337 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L29/785

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a first dielectric layer, a work function layer, and a gate electrode sequentially stacked over the substrate, the first dielectric layer has a thin portion and a thick portion, the thin portion is thinner than the thick portion and surrounds the thick portion, and the first dielectric layer is a single-layer structure. The semiconductor device structure includes an insulating layer over the substrate and wrapping around the gate stack. The thin portion is between the thick portion and the insulating layer.

公开(公告)号：US12051595B2

公开(公告)日：2024-07-30

申请号：US17669944

申请日：2022-02-11

Applicant: TOKYO ELECTRON LIMITED

Inventor： Masahiro Tabata

IPC: H01J37/32 ,  H01L21/02 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/67

CPC classification number: H01L21/31116 ,  H01J37/32449 ,  H01L21/0212 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/0234 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/67069 ,  H01J2237/3321 ,  H01J2237/3341

Abstract: A plasma processing method executed by a plasma processing apparatus includes a first step, a second step, and an etching step. In the first step, the plasma processing apparatus forms a first film on a processing target in which a plurality of openings having a predetermined pattern are formed. In the second step, the plasma processing apparatus forms a second film having an etching rate lower than that of the first film on the processing target on which the first film is formed, and having different film thicknesses on the side surfaces of the openings according to the sizes of the openings. In the etching step, the plasma processing apparatus performs etching from above the second film under a predetermined processing condition until a portion of the first film is removed from at least a portion of the processing target.

公开(公告)号：US20240162351A1

公开(公告)日：2024-05-16

申请号：US18509825

申请日：2023-11-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kengo AKIMOTO

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/24 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/02565 ,  H01L29/247 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

Abstract: An object is to provide favorable interface characteristics of a thin film transistor including an oxide semiconductor layer without mixing of an impurity such as moisture. Another object is to provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability, and a method by which a semiconductor device can be manufactured with high productivity. A main point is to perform oxygen radical treatment on a surface of a gate insulating layer. Accordingly, there is a peak of the oxygen concentration at an interface between the gate insulating layer and a semiconductor layer, and the oxygen concentration of the gate insulating layer has a concentration gradient. The oxygen concentration is increased toward the interface between the gate insulating layer and the semiconductor layer.

公开(公告)号：US20240102170A1

公开(公告)日：2024-03-28

申请号：US18370752

申请日：2023-09-20

Applicant: LoMaRe Chip Technology Changzhou Co., Ltd. ,  LoMaRe Technologies Limited

Inventor： Fengzhi Yu ,  Xudong Sun ,  Andrei Paul Mihai ,  Bin Zou ,  Jan Zemen ,  Kapildeb Dolui

IPC: C23C16/56 ,  C23C16/30 ,  H01G7/06 ,  H01L21/02

CPC classification number: C23C16/56 ,  C23C16/30 ,  H01G7/06 ,  H01L21/02197 ,  H01L21/0228 ,  H01L21/0234 ,  H01L28/55

Abstract: The present invention provides a high-crystallinity barium titanate film structure, a method of preparation and an application thereof, and relates to the field of materials and devices. The method includes the steps of depositing, on a substrate, a barium titanate layer with a (001) or (111) crystal orientation by atomic layer deposition in a high vacuum environment and at a low temperature of 450° C. or below, wherein a Ba/Ti ratio in the barium titanate layer is 0.9-1.5; and performing plasma annealing treatment on the barium titanate layer at a low temperature of 450° C. or below without breaking vacuum to form a high-crystallinity barium titanate layer having the (001) or (111) crystal orientation. The film structure may further comprise top and bottom electrodes formed above and below the barium titanate layer. The present invention solves the problem that an existing method for obtaining a crystalline BTO film is not applicable to back-end of line (BEOL) integration processes.

公开(公告)号：US20240079230A1

公开(公告)日：2024-03-07

申请号：US18079069

申请日：2022-12-12

Applicant: METAL INDUSTRIES RESEARCH & DEVELOPMENT CENTRE

Inventor： Wei-Chen Tien ,  Cheng-Yuan Hung ,  Chang-Sin Ye ,  Chun-Kai Huang ,  Yii-Der Wu

IPC: H01L21/02 ,  H01J37/32

CPC classification number: H01L21/0234 ,  H01J37/32449 ,  H01J37/32522 ,  H01J37/32834 ,  H01L21/02178

Abstract: A plasma-assisted annealing system includes a high temperature furnace, a plasma-induced dissociator and a connecting duct. The plasma-induced dissociator is provided to dissociate a working gas and exhaust the dissociated working gas from its working gas outlet. Both ends of the connecting duct are connected to the working gas outlet of the plasma-induced dissociator and a gas inlet of the high temperature furnace, respectively. The working gas dissociated in the plasma-induced dissociator is introduced into the high temperature furnace via the connecting duct.