公开(公告)号：US20190013394A1

公开(公告)日：2019-01-10

申请号：US16121567

申请日：2018-09-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tan-Ya Yin ,  Chia-Wei Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a patterned metal gate layer. The substrate includes a first fin segment and a second fin segment respectively protruding from a top surface of the substrate. The first fin segment and the second fin segment respectively extend along a first direction and are arranged along a second direction, the first fin segment comprises a first fin structure at an end of the first segment, and the second fin segment comprises a first recess at an end of the second fin segment, and the first recess and the first fin structure are arranged along the second direction. The patterned metal gate layer is disposed on the substrate, and the patterned metal gate layer covers the first fin structure.

公开(公告)号：US10446663B2

公开(公告)日：2019-10-15

申请号：US16121567

申请日：2018-09-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tan-Ya Yin ,  Chia-Wei Huang

IPC: H01L31/119 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/308 ,  H01L29/06

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a patterned metal gate layer. The substrate includes a first fin segment and a second fin segment respectively protruding from a top surface of the substrate. The first fin segment and the second fin segment respectively extend along a first direction and are arranged along a second direction, the first fin segment comprises a first fin structure at an end of the first fin segment, and the second fin segment comprises a first recess at an end of the second fin segment, and the first recess and the first fin structure are arranged along the second direction. The patterned metal gate layer is disposed on the substrate, and the patterned metal gate layer covers the first fin structure.

公开(公告)号：US09368365B1

公开(公告)日：2016-06-14

申请号：US14709488

申请日：2015-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hsun Kuo ,  Ting-Cheng Tseng ,  Tan-Ya Yin ,  Chia-Wei Huang ,  Ming-Jui Chen

IPC: H01L21/30 ,  H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/66795

Abstract: A manufacturing method for forming a semiconductor structure includes: first, a plurality of fin structures are formed on a substrate and arranged along a first direction, next, a first fin cut process is performed, so as to remove parts of the fin structures which are disposed within at least one first fin cut region, and a second fin cut process is then performed, so as to remove parts of the fin structures which are disposed within at least one second fin cut region, where the second fin cut region is disposed along at least one edge of the first fin cut region.

Abstract translation: 一种用于形成半导体结构的制造方法，其特征在于：首先，在基板上形成多个翅片结构，沿第一方向配置，接着，进行第一翅片切割加工， 设置在至少一个第一翅片切割区域内，然后执行第二翅片切割过程，以便去除设置在至少一个第二翅片切割区域内的翅片结构的部分，其中第二翅片切割区域沿着 第一鳍片切割区域的至少一个边缘。

公开(公告)号：US20170162449A1

公开(公告)日：2017-06-08

申请号：US15434067

申请日：2017-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Wei-Cyuan Lo ,  Ming-Jui Chen ,  Chia-Lin Lu ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Tan-Ya Yin ,  Chia-Wei Huang ,  Shu-Ru Wang ,  Yung-Feng Cheng

IPC: H01L21/8238 ,  H01L27/11 ,  H01L23/535 ,  H01L21/768 ,  H01L27/092

CPC classification number: H01L21/823871 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/485 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.

公开(公告)号：US20170018302A1

公开(公告)日：2017-01-19

申请号：US14822911

申请日：2015-08-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tan-Ya Yin ,  Ming-Jui Chen ,  Chia-Wei Huang ,  Yu-Cheng Tung ,  Chin-Sheng Yang

IPC: G11C11/412 ,  H01L27/02 ,  H01L27/11

CPC classification number: G11C11/417 ,  G11C11/412 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104

Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.

Abstract translation: 静态随机存取存储器单元结构和布局结构包括两个上拉晶体管，两个下拉晶体管，两个槽接触插头和两个金属零互连。 每个金属零互连设置在每个槽接触插头和每个上拉晶体管的栅极上，每个槽接触插塞跨越每个下拉晶体管的漏极和每个上拉晶体管的漏极延伸到 跨越每个金属零互连的一端。 槽接触插塞之间的间隙小于金属零互连之间的间隙。

公开(公告)号：US10153034B2

公开(公告)日：2018-12-11

申请号：US15448599

申请日：2017-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tan-Ya Yin ,  Ming-Jui Chen ,  Chia-Wei Huang ,  Yu-Cheng Tung ,  Chin-Sheng Yang

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/11 ,  G11C11/417 ,  G11C11/412

Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.

公开(公告)号：US10109720B1

公开(公告)日：2018-10-23

申请号：US15618141

申请日：2017-06-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tan-Ya Yin ,  Chia-Wei Huang

IPC: H01L29/768 ,  H01L29/80 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L21/308

CPC classification number: H01L29/66545 ,  H01L21/3085 ,  H01L29/0692 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a patterned conductive layer and an epitaxial layer. The substrate includes a first fin structure and a second fin structure respectively protruding from a top surface of the substrate, and the second fin structure has a recess. The patterned conductive layer is disposed on the substrate and covers a first end of the first fin structure. The epitaxial layer is disposed in the recess. The first end of the first fin structure and a second end of the epitaxial layer face a first direction.

公开(公告)号：US09859170B2

公开(公告)日：2018-01-02

申请号：US15434067

申请日：2017-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Wei-Cyuan Lo ,  Ming-Jui Chen ,  Chia-Lin Lu ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Tan-Ya Yin ,  Chia-Wei Huang ,  Shu-Ru Wang ,  Yung-Feng Cheng

IPC: H01L21/8238 ,  H01L21/768 ,  H01L27/11 ,  H01L23/535 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823871 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/485 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.

公开(公告)号：US09627036B2

公开(公告)日：2017-04-18

申请号：US14822911

申请日：2015-08-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tan-Ya Yin ,  Ming-Jui Chen ,  Chia-Wei Huang ,  Yu-Cheng Tung ,  Chin-Sheng Yang

IPC: H01L21/28 ,  H01L23/535 ,  H01L27/11 ,  H01L29/66 ,  G11C11/412 ,  H01L27/02

CPC classification number: G11C11/417 ,  G11C11/412 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104

Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.

公开(公告)号：US20180308954A1

公开(公告)日：2018-10-25

申请号：US15618141

申请日：2017-06-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tan-Ya Yin ,  Chia-Wei Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L21/308

CPC classification number: H01L29/66545 ,  H01L21/3085 ,  H01L29/0692 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a patterned conductive layer and an epitaxial layer. The substrate includes a first fin structure and a second fin structure respectively protruding from a top surface of the substrate, and the second fin structure has a recess. The patterned conductive layer is disposed on the substrate and covers a first end of the first fin structure. The epitaxial layer is disposed in the recess. The first end of the first fin structure and a second end of the epitaxial layer face a first direction.