公开(公告)号：US20240405017A1

公开(公告)日：2024-12-05

申请号：US18325376

申请日：2023-05-30

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Sunglyong Kim ,  Kyoung Min Lee

IPC: H01L27/06 ,  H01L29/66

Abstract: A microelectronic device including an integrated boot diode and a depleted mode LDMOS transistor with a charge balance layer isolated from the body region and electrically in contact with a substrate. The connection of the charge balance layer of the depleted mode LDMOS transistor directly to the substrate or ground reference eliminates body diode turn-on from the body of the transistor to the drain which typically happens above approximately 0.7 volts. In addition, the depleted mode LDMOS transistor may separate a source contact from a body contact which allows a negative bias of the body with respect to the source. Typically, the source voltage is limited to approximately 7 volts before parasitic PNP turn on becomes a factor. By negatively biasing the body with respect to the source, the maximum source voltage of the depleted mode LDMOS transistor without PNP parasitic turn-on may be increased to approximately 30 V.

公开(公告)号：US20240363394A1

公开(公告)日：2024-10-31

申请号：US18141153

申请日：2023-04-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Sunglyong Kim ,  Meng-Chia Lee ,  Satoshi Suzuki ,  Seetharaman Sridhar

IPC: H01L21/761 ,  H01L27/088

CPC classification number: H01L21/761 ,  H01L27/088 ,  H01L21/2652 ,  H01L21/266 ,  H01L29/66681

Abstract: Described examples include an integrated circuit having a substrate, a first doped region in the substrate having a first conductivity type, and a first epitaxial layer on the substrate, wherein the first doped region extends into the first epitaxial layer. The integrated circuit also has a second doped region in the first epitaxial layer having the first conductivity type, a second epitaxial layer on the first epitaxial layer, wherein the second doped region extends into the second epitaxial layer. The integrated circuit also has a well in the second epitaxial layer having a second conductivity type, and a first active device formed in the well.

公开(公告)号：US20210143145A1

公开(公告)日：2021-05-13

申请号：US17123413

申请日：2020-12-16

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  David LaFonteese ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

公开(公告)号：US20200075576A1

公开(公告)日：2020-03-05

申请号：US16677044

申请日：2019-11-07

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  David LaFonteese ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L27/02 ,  H01L29/08 ,  H01L29/78 ,  H01L29/10

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

公开(公告)号：US10559681B2

公开(公告)日：2020-02-11

申请号：US15850854

申请日：2017-12-21

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L29/78 ,  H01L21/28 ,  H03K17/687 ,  H01L29/10 ,  H01L21/761 ,  H01L29/49 ,  H01L29/66 ,  H01L29/06

Abstract: A lateral junction diode device includes a substrate having at least a semiconductor surface layer. A depletion-mode LDMOS device is in the semiconductor surface layer including a source, drain, and a gate above a gate dielectric, and a channel region under the gate on the gate dielectric. A drift region is between the channel region and the drain, wherein the drain also provides a cathode for the lateral junction diode device. An embedded diode includes a second cathode and an anode that is shared with the device. The embedded diode is junction isolated by an isolation region located between the anode and the source. The anode and isolation region are directly connected to the gate and the second cathode is directly connected to the source.

公开(公告)号：US12094970B2

公开(公告)日：2024-09-17

申请号：US17174023

申请日：2021-02-11

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  Seetharaman Sridhar ,  Sameer Pendharkar ,  David LaFonteese

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H02H9/04 ,  H03K19/0185

CPC classification number: H01L29/7816 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0266 ,  H01L27/027 ,  H01L27/0285 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/7835 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/42368 ,  H02H9/044 ,  H02H9/046 ,  H03K19/018507

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a p-channel device and an n-channel device. The p-channel device includes an n-type barrier region circumscribing a p-type drain region with an n-type body region. The p-channel device may be positioned adjacent to the n-channel device and a high voltage junction diode.

公开(公告)号：US20230087151A1

公开(公告)日：2023-03-23

申请号：US17502692

申请日：2021-10-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Thomas Grebs ,  Meng-Chia Lee ,  Hong Yang ,  Ya ping Chen ,  Sunglyong Kim

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66

Abstract: A trench gate metal oxide semiconductor (MOSFET) device includes a substrate with a semiconductor surface layer doped a first conductivity type. At least one trench gate MOSFET cell is located in or over the semiconductor surface layer, and includes a body region in the semiconductor surface layer doped a second conductivity type, and a source region on top of the body region doped the first conductivity type. A trench extends down from a top side of the semiconductor surface layer, the trench abutting the body region and being lined with a dielectric material. A field plate that includes polysilicon is located in the trench, and a gate electrode is located over the field plate. The field plate has a bottom portion, a middle portion, and a top portion, wherein the bottom portion is narrower than the middle portion, and the middle portion is narrower than the top portion.

公开(公告)号：US20230061337A1

公开(公告)日：2023-03-02

申请号：US17463529

申请日：2021-08-31

Applicant: Texas Instruments Incorporated

Inventor： Jungwoo Joh ,  Sunglyong Kim ,  Seetharaman Sridhar ,  Sameer Pendharkar ,  James Craig Ondrusek ,  Srikanth Krishnan

IPC: H01L29/417 ,  H01L23/482 ,  H01L27/098

Abstract: An integrated circuit, including a source region, a drain region, a channel region between the source region and the drain region, and a gate for inducing a conductive path through the channel region. The integrated circuit also includes structure, proximate a curved length of the gate, for inhibiting current flow along a portion of the channel region.

公开(公告)号：US20210167206A1

公开(公告)日：2021-06-03

申请号：US17174023

申请日：2021-02-11

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  Seetharaman Sridhar ,  Sameer Pendharkar ,  David LaFonteese

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a p-channel device and an n-channel device. The p-channel device includes an n-type barrier region circumscribing a p-type drain region with an n-type body region. The p-channel device may be positioned adjacent to the n-channel device and a high voltage junction diode.

公开(公告)号：US10936000B1

公开(公告)日：2021-03-02

申请号：US16552739

申请日：2019-08-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Ryan Hanschke ,  Filippo Marino ,  Sunglyong Kim ,  Tobin Daniel Hagan ,  Richard Lee Valley ,  Bharath Balaji Kannan ,  Salvatore Giombanco ,  Seetharaman Sridhar

IPC: G05F1/10 ,  G05F3/02 ,  G05F1/575 ,  G05F1/565

Abstract: In an example, a circuit includes a first power switch device coupled between a voltage input and an output terminal, the first power switch device having a control input. A voltage divider circuit includes a first resistor and a second resistor. The first resistor is coupled between the voltage input and a sense node between the first resistor and the second resistor. The second resistor has a first terminal coupled to the sense node and a second terminal. A second switch device is coupled between the second terminal of the second resistor and an electrical ground terminal. A voltage clamp is coupled between the sense node and the electrical ground terminal.