-
公开(公告)号：US10936000B1
公开(公告)日：2021-03-02
申请号：US16552739
申请日：2019-08-27
发明人： Michael Ryan Hanschke , Filippo Marino , Sunglyong Kim , Tobin Daniel Hagan , Richard Lee Valley , Bharath Balaji Kannan , Salvatore Giombanco , Seetharaman Sridhar
摘要： In an example, a circuit includes a first power switch device coupled between a voltage input and an output terminal, the first power switch device having a control input. A voltage divider circuit includes a first resistor and a second resistor. The first resistor is coupled between the voltage input and a sense node between the first resistor and the second resistor. The second resistor has a first terminal coupled to the sense node and a second terminal. A second switch device is coupled between the second terminal of the second resistor and an electrical ground terminal. A voltage clamp is coupled between the sense node and the electrical ground terminal.
-
公开(公告)号：US10554200B2
公开(公告)日：2020-02-04
申请号：US16214770
申请日：2018-12-10
IPC分类号： H02M1/42 , H03K5/1532 , H02M1/32
摘要： Peak detection methods, apparatus, and circuits are disclosed. An example peak detector includes a first peak-hold circuit having a first input terminal and a first output terminal, the first peak-hold circuit to determine a first peak of a rectified input voltage at the first input terminal during a first time interval, and to track a second peak of the rectified input voltage during a second time interval, the second time interval distinct from the first time interval, and a second peak-hold circuit having a second input terminal and a second output terminal, the second peak-hold circuit to determine, during the second time interval, a greater of the first peak and the second peak, the first output terminal coupled to the second input terminal, the greater of the first peak and the second peak output at the second output terminal.
-
公开(公告)号：US20240272670A1
公开(公告)日：2024-08-15
申请号：US18645579
申请日：2024-04-25
CPC分类号： G06F1/14 , G06F11/1604 , H04L7/0037 , H04L7/0045
摘要： A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a particular duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.
-
公开(公告)号：US20200219872A1
公开(公告)日：2020-07-09
申请号：US16240356
申请日：2019-01-04
发明人： Sunglyong Kim , Richard Lee Valley , Tobin Daniel Hagan , Michael Ryan Hanschke , Seetharaman Sridhar
IPC分类号： H01L27/07 , H01L49/02 , H01L29/78 , H01L29/16 , H01L21/8238
摘要： Described examples include a semiconductor device having a resistor. The resistor includes a first terminal and a second terminal. The resistor also includes a first resistive element over an insulating layer over a substrate having a first end coupled to the first terminal of the resistor and a second end coupled to the second terminal of the resistor; and a parallel second resistive element over the insulating layer over the substrate having a first end coupled to the first terminal of the resistor and a second end coupled to the second terminal of the resistor. The resistor may also be coupled in series with another resistor.
-
公开(公告)号：US20220308618A1
公开(公告)日：2022-09-29
申请号：US17841255
申请日：2022-06-15
摘要： A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a particular duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.
-
公开(公告)号：US10186964B1
公开(公告)日：2019-01-22
申请号：US15943415
申请日：2018-04-02
发明人： Michael Ryan Hanschke , Salvatore Giombanco , John C. Vogt , Filippo Marino , Joseph Michael Leisten , Ananthakrishnan Viswanathan
摘要： At least some aspects of the present disclosure provide for a circuit. In one example, the circuit includes a logic circuit having multiple inputs and multiple outputs, a calculated discontinuous conduction (DCM) (TDCM) timer having an input coupled to one of the logic circuit outputs and an output coupled to one of the logic circuit inputs, an on-time (TON) timer having an input coupled to one of the logic circuit outputs and an output coupled to one of the logic circuit inputs, and a hysteresis timer having an input coupled to one of the logic circuit outputs and multiple outputs coupled to multiple of the logic circuit inputs.
-
公开(公告)号：US20210096592A1
公开(公告)日：2021-04-01
申请号：US17039260
申请日：2020-09-30
摘要： A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a predetermined duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.
-
公开(公告)号：US20200007115A1
公开(公告)日：2020-01-02
申请号：US16214770
申请日：2018-12-10
IPC分类号： H03K5/1532 , H02M1/32 , H02M1/42
摘要： Peak detection methods, apparatus, and circuits are disclosed. An example peak detector includes a first peak-hold circuit having a first input terminal and a first output terminal, the first peak-hold circuit to determine a first peak of a rectified input voltage at the first input terminal during a first time interval, and to track a second peak of the rectified input voltage during a second time interval, the second time interval distinct from the first time interval, and a second peak-hold circuit having a second input terminal and a second output terminal, the second peak-hold circuit to determine, during the second time interval, a greater of the first peak and the second peak, the first output terminal coupled to the second input terminal, the greater of the first peak and the second peak output at the second output terminal.
-
公开(公告)号：US11994901B2
公开(公告)日：2024-05-28
申请号：US17841255
申请日：2022-06-15
CPC分类号： G06F1/14 , G06F11/1604 , H04L7/0037 , H04L7/0045
摘要： A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a particular duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.
-
公开(公告)号：US11385677B2
公开(公告)日：2022-07-12
申请号：US17039260
申请日：2020-09-30
摘要： A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a predetermined duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.
-
-
-
-
-
-
-
-
-
搜索结果
12 条记录 (耗时 0.017 秒)
