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公开(公告)号：US11025242B2
公开(公告)日：2021-06-01
申请号：US16933453
申请日：2020-07-20
发明人： Sarvesh Bang , Arun Rao , Joseph Pham
IPC分类号： H03K17/08 , H03K17/04 , H03K5/08 , H03K17/0812
摘要： Methods, apparatus, systems and articles of manufacture are disclosed to transmit signal in isolated gate drivers. An example apparatus includes a first encoder including: an edge detector coupled to a first sensor; a first clock counter coupled to the edge detector; a first signal selector coupled to the first clock counter; and a first multiplexer including coupled to a signal generator, the first clock counter, and the first signal selector; and a second encoder including: a level detector coupled to a second sensor; a second clock counter coupled to the level detector; a second signal selector coupled to the level detector and the second clock counter; and a second multiplexer coupled to the first multiplexer, a reference voltage, the second signal selector, and a modulator.
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公开(公告)号：US20220308618A1
公开(公告)日：2022-09-29
申请号：US17841255
申请日：2022-06-15
摘要： A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a particular duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.
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公开(公告)号：US20240272670A1
公开(公告)日：2024-08-15
申请号：US18645579
申请日：2024-04-25
CPC分类号： G06F1/14 , G06F11/1604 , H04L7/0037 , H04L7/0045
摘要： A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a particular duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.
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公开(公告)号：US20210250021A1
公开(公告)日：2021-08-12
申请号：US17244712
申请日：2021-04-29
发明人： Sarvesh Bang , Arun Rao , Joseph Pham
IPC分类号： H03K17/0812
摘要： Methods, apparatus, systems and articles of manufacture are disclosed to transmit signal in isolated gate drivers. An example apparatus includes a first encoder including: an edge detector coupled to a first sensor; a first clock counter coupled to the edge detector; a first signal selector coupled to the first clock counter; and a first multiplexer including coupled to a signal generator, the first clock counter, and the first signal selector; and a second encoder including: a level detector coupled to a second sensor; a second clock counter coupled to the level detector; a second signal selector coupled to the level detector and the second clock counter; and a second multiplexer coupled to the first multiplexer, a reference voltage, the second signal selector, and a modulator.
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公开(公告)号：US11799466B2
公开(公告)日：2023-10-24
申请号：US17244712
申请日：2021-04-29
发明人： Sarvesh Bang , Arun Rao , Joseph Pham
IPC分类号： H03K17/0812
CPC分类号： H03K17/08122
摘要： Methods, apparatus, systems and articles of manufacture are disclosed to transmit signal in isolated gate drivers. An example apparatus includes a first encoder including: an edge detector coupled to a first sensor; a first clock counter coupled to the edge detector; a first signal selector coupled to the first clock counter; and a first multiplexer including coupled to a signal generator, the first clock counter, and the first signal selector; and a second encoder including: a level detector coupled to a second sensor; a second clock counter coupled to the level detector; a second signal selector coupled to the level detector and the second clock counter; and a second multiplexer coupled to the first multiplexer, a reference voltage, the second signal selector, and a modulator.
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公开(公告)号：US20210096592A1
公开(公告)日：2021-04-01
申请号：US17039260
申请日：2020-09-30
摘要： A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a predetermined duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.
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公开(公告)号：US20200076416A1
公开(公告)日：2020-03-05
申请号：US16552805
申请日：2019-08-27
发明人： Sarvesh Bang , Arun Rao , Joseph Pham
IPC分类号： H03K17/0812
摘要： Methods, apparatus, systems and articles of manufacture are disclosed to transmit signals in isolated gate drivers. An example apparatus includes a first encoder including: an edge detector coupled to a first sensor; a first clock counter coupled to the edge detector; a first signal selector coupled to the first clock counter; and a first multiplexer coupled to a signal generator, the first clock counter, and the first signal selector; and a second encoder including: a level detector coupled to a second sensor; a second clock counter coupled to the level detector; a second signal selector coupled to the level detector and the second clock counter; and a second multiplexer coupled to the first multiplexer, a reference voltage, the second signal selector, and a modulator.
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公开(公告)号：US11994901B2
公开(公告)日：2024-05-28
申请号：US17841255
申请日：2022-06-15
CPC分类号： G06F1/14 , G06F11/1604 , H04L7/0037 , H04L7/0045
摘要： A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a particular duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.
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公开(公告)号：US11385677B2
公开(公告)日：2022-07-12
申请号：US17039260
申请日：2020-09-30
摘要： A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a predetermined duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.
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公开(公告)号：US20200350905A1
公开(公告)日：2020-11-05
申请号：US16933453
申请日：2020-07-20
发明人： Sarvesh Bang , Arun Rao , Joseph Pham
IPC分类号： H03K17/0812
摘要： Methods, apparatus, systems and articles of manufacture are disclosed to transmit signal in isolated gate drivers. An example apparatus includes a first encoder including: an edge detector coupled to a first sensor; a first clock counter coupled to the edge detector; a first signal selector coupled to the first clock counter; and a first multiplexer including coupled to a signal generator, the first clock counter, and the first signal selector; and a second encoder including: a level detector coupled to a second sensor; a second clock counter coupled to the level detector; a second signal selector coupled to the level detector and the second clock counter; and a second multiplexer coupled to the first multiplexer, a reference voltage, the second signal selector, and a modulator.
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