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公开(公告)号：US11011975B2
公开(公告)日：2021-05-18
申请号：US16221419
申请日：2018-12-14
摘要： In an example, a system comprises a boost power factor correction (PFC) converter including a thermistor, an inductor, and a transistor coupled to a common node. The system also comprises a PFC controller coupled to the common node. The PFC controller includes a comparator coupled to a threshold voltage source and to a non-control terminal of the transistor; a first flip-flop coupled to the comparator and to a control terminal of the transistor; a zero current detector coupled to the inductor; a timer coupled to the comparator and to the zero current detector; a second flip-flop coupled to the timer and to the control terminal of the transistor; an AND gate coupled to the first and second flip-flops; a third flip-flop coupled to the second flip-flop and to the control terminal of the transistor; and a fourth flip-flop coupled to the AND gate and to the control terminal of the transistor.
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公开(公告)号：US20170264289A1
公开(公告)日：2017-09-14
申请号：US15067928
申请日：2016-03-11
发明人： Yongxi Zhang , Sameer P. Pendharkar , Philip L. Hower , Salvatore Giombanco , Filippo Marino , Seetharaman Sridhar
IPC分类号： H03K17/687 , H01L29/06 , H03K19/0185 , H01L27/092
CPC分类号： H03K19/018521 , H01L21/823807 , H01L21/823814 , H01L27/092 , H01L29/0634 , H01L29/0696 , H01L29/1033 , H01L29/7816 , H01L29/7831 , H03K17/122
摘要： An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.
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公开(公告)号：US11671006B2
公开(公告)日：2023-06-06
申请号：US17232974
申请日：2021-04-16
CPC分类号： H02M1/4225 , H02M1/0038 , H02M1/32
摘要： In an example, a system comprises a boost power factor correction (PFC) converter that includes a thermistor, an inductor, and a transistor and a PFC controller coupled to a common node. The PFC controller includes a comparator coupled to a threshold voltage source and to a terminal of the transistor. A first flip-flop is coupled to the comparator and to a control terminal of the transistor. A zero current detector is coupled to the inductor. A timer is coupled to the comparator and to the zero current detector. A second flip-flop is coupled to the timer and to the control terminal of the transistor. An AND gate is coupled to the first and second flip-flops. The circuit includes third and fourth flip flops.
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公开(公告)号：US09843322B2
公开(公告)日：2017-12-12
申请号：US15067928
申请日：2016-03-11
发明人： Yongxi Zhang , Sameer P. Pendharkar , Philip L. Hower , Salvatore Giombanco , Filippo Marino , Seetharaman Sridhar
IPC分类号： H03L5/00 , H03K17/687 , H01L27/092 , H01L29/06 , H03K19/0185
CPC分类号： H03K19/018521 , H01L21/823807 , H01L21/823814 , H01L27/092 , H01L29/0634 , H01L29/0696 , H01L29/1033 , H01L29/7816 , H01L29/7831 , H03K17/122
摘要： An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.
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公开(公告)号：US10784785B2
公开(公告)日：2020-09-22
申请号：US15850177
申请日：2017-12-21
摘要： A switch-mode power supply includes a power transistor, a transformer, and detection circuitry. The transformer includes a primary winding that is coupled to a drain terminal of the power transistor. The detection circuitry is coupled to a source terminal of the power transistor. The detection circuitry is operable to monitor signal present on the drain terminal via parasitic drain-source capacitance of the power transistor while the power transistor is switched off, and to detect demagnetization of a secondary winding of the transformer via the monitored signal.
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公开(公告)号：US10601422B2
公开(公告)日：2020-03-24
申请号：US15809291
申请日：2017-11-10
发明人： Yongxi Zhang , Sameer P. Pendharkar , Philip L. Hower , Salvatore Giombanco , Filippo Marino , Seetharaman Sridhar
IPC分类号： H03K17/687 , H01L29/06 , H03K19/0185 , H01L29/78 , H01L29/10 , H03K17/12 , H01L27/092 , H01L21/8238
摘要： An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.
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公开(公告)号：US10186964B1
公开(公告)日：2019-01-22
申请号：US15943415
申请日：2018-04-02
发明人： Michael Ryan Hanschke , Salvatore Giombanco , John C. Vogt , Filippo Marino , Joseph Michael Leisten , Ananthakrishnan Viswanathan
摘要： At least some aspects of the present disclosure provide for a circuit. In one example, the circuit includes a logic circuit having multiple inputs and multiple outputs, a calculated discontinuous conduction (DCM) (TDCM) timer having an input coupled to one of the logic circuit outputs and an output coupled to one of the logic circuit inputs, an on-time (TON) timer having an input coupled to one of the logic circuit outputs and an output coupled to one of the logic circuit inputs, and a hysteresis timer having an input coupled to one of the logic circuit outputs and multiple outputs coupled to multiple of the logic circuit inputs.
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公开(公告)号：US20180097517A1
公开(公告)日：2018-04-05
申请号：US15809291
申请日：2017-11-10
发明人： Yongxi Zhang , Sameer P. Pendharkar , Philip L. Hower , Salvatore Giombanco , Filippo Marino , Seetharaman Sridhar
IPC分类号： H03K17/687 , H01L27/092 , H01L29/06 , H03K19/0185
CPC分类号： H03K19/018521 , H01L21/823807 , H01L21/823814 , H01L27/092 , H01L29/0634 , H01L29/0696 , H01L29/1033 , H01L29/7831 , H01L29/7835 , H03K17/122
摘要： An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.
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公开(公告)号：US10936000B1
公开(公告)日：2021-03-02
申请号：US16552739
申请日：2019-08-27
发明人： Michael Ryan Hanschke , Filippo Marino , Sunglyong Kim , Tobin Daniel Hagan , Richard Lee Valley , Bharath Balaji Kannan , Salvatore Giombanco , Seetharaman Sridhar
摘要： In an example, a circuit includes a first power switch device coupled between a voltage input and an output terminal, the first power switch device having a control input. A voltage divider circuit includes a first resistor and a second resistor. The first resistor is coupled between the voltage input and a sense node between the first resistor and the second resistor. The second resistor has a first terminal coupled to the sense node and a second terminal. A second switch device is coupled between the second terminal of the second resistor and an electrical ground terminal. A voltage clamp is coupled between the sense node and the electrical ground terminal.
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公开(公告)号：US10141852B2
公开(公告)日：2018-11-27
申请号：US15395795
申请日：2016-12-30
摘要： A circuit for use in an LLC converter to control diode conduction time includes a secondary side controller, the secondary side controller configured to monitor voltage, measure a diode conduction time for the LLC converter, in response to determining that the diode conduction time is greater that a target time, increase the on-time for the first switch, and in response to determining that the diode conduction time is less than a target time, decrease the on-time for the first switch.
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