公开(公告)号：US20230060543A1

公开(公告)日：2023-03-02

申请号：US17461688

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tz-Shian CHEN ,  Yi-Chao WANG ,  Wen-Yen CHEN ,  Li-Ting WANG ,  Huicheng CHANG ,  Yee-Chia YEO

IPC: G01K11/125 ,  H01L21/67 ,  H01L21/66

Abstract: A temperature measuring apparatus for measuring a temperature of a substrate is described. A light emitting source that emits light signals such as laser pulses are applied to the substrate. A detector on the other side of the light emitting source receives the reflected laser pulses. The detector further receives emission signals associated with temperature or energy density that is radiated from the surface of the substrate. The temperature measuring apparatus determines the temperature of the substrate during a thermal process using the received laser pulses and the emission signals. To improve the signal to noise ratio of the reflected laser pulses, a polarizer may be used to polarize the laser pulses to have a S polarization. The angle in which the polarized laser pulses are applied towards the substrate may also be controlled to enhance the signal to noise ratio at the detector's end.

公开(公告)号：US20220157936A1

公开(公告)日：2022-05-19

申请号：US17097959

申请日：2020-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal Abhijith KHADERBAD ,  Dhanyakumar Mahaveer SATHAIYA ,  Huicheng CHANG ,  Ko-Feng CHEN ,  Keng-Chu LIN

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

Abstract: The present disclosure is directed to a method for the fabrication of isolation structures between source/drain (S/D)) epitaxial structures of stacked transistor structures. The method includes depositing an oxygen-free dielectric material in an opening over a first epitaxial structure, where the oxygen-free dielectric material covers top surfaces of the first epitaxial structure and sidewall surfaces of the opening. The method also includes exposing the oxygen-free dielectric material to an oxidizing process to oxidize the oxygen-free dielectric material so that the oxidizing process does not oxidize a portion of the oxygen-free dielectric material on the first epitaxial structure. Further, etching the oxidized oxygen-free dielectric material and forming a second epitaxial layer on the oxygen-free dielectric material not removed by the etching to substantially the opening.

公开(公告)号：US20210159226A1

公开(公告)日：2021-05-27

申请号：US17170601

申请日：2021-02-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chang LIN ,  Chun-Feng NIEH ,  Huicheng CHANG ,  Hou-Yu CHEN ,  Yong-Yan LU

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/12 ,  H01L21/84 ,  H01L29/49

Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

公开(公告)号：US20180350984A1

公开(公告)日：2018-12-06

申请号：US16049358

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Carlos H. DIAZ ,  Chun-Hsiung LIN ,  Huicheng CHANG ,  Syun-Ming JANG ,  Chien-Hsun WANG ,  Mao-Lin HUANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/775 ,  H01L29/66 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/778 ,  H01L29/165 ,  H01L29/51

CPC classification number: H01L29/7842 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/78696

Abstract: In a method of manufacturing a semiconductor device, a support layer is formed over a substrate. A patterned semiconductor layer made of a first semiconductor material is formed over the support layer. A part of the support layer under a part of the semiconductor layer is removed, thereby forming a semiconductor wire. A semiconductor shell layer made of a second semiconductor material different from the first semiconductor material is formed around the semiconductor wire.

公开(公告)号：US20190305107A1

公开(公告)日：2019-10-03

申请号：US15939389

申请日：2018-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju CHEN ,  Su-Hao LIU ,  Chun-Hao KUNG ,  Liang-Yin CHEN ,  Huicheng CHANG ,  Kei-Wei CHEN ,  Hui-Chi HUANG ,  Kao-Feng LIAO ,  Chih-Hung CHEN ,  Jie-Huang HUANG ,  Lun-Kuang TAN ,  Wei-Ming YOU

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a source/drain structure, a dielectric layer, a contact plug. The gate structure is positioned over a fin structure. The source/drain structure is positioned in the fin structure and adjacent to the gate structure. The dielectric layer is positioned over the gate structure and the source/drain structure. The contact plug is positioned passing through the dielectric layer. The contact plug includes a first metal compound including one of group III elements, group IV elements, group V elements or a combination thereof.

公开(公告)号：US20190157156A1

公开(公告)日：2019-05-23

申请号：US15964862

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Ju CHEN ,  Xiong-Fei YU ,  Chi-On CHUI ,  Yee-Chia YEO ,  Huicheng CHANG

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/762

Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming a first fin and a second fin over a substrate, and conformally forming a silicon oxide layer over the first fin using a first atomic layer deposition (ALD) process. The method also includes conformally forming a silicon nitride layer over the silicon oxide layer using a second ALD process, and forming an insulating layer to fill the trench between the first fin and the second fin over the substrate. The method further includes recessing the insulating layer, the silicon oxide layer, and the silicon nitride layer to form an isolation structure with a liner. In addition, the method includes forming a gate structure over the first fin, and forming a source region and a drain region in the first fin and on opposite sides of the gate structure.

公开(公告)号：US20190027473A1

公开(公告)日：2019-01-24

申请号：US15652719

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng CHEN ,  Chia-Ling CHAN ,  Liang-Yin CHEN ,  Huicheng CHANG

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66

Abstract: A semiconductor device and a method for forming the same are provided. The semiconductor device includes a gate structure and a source/drain feature. The gate structure is positioned over a fin structure. The source/drain feature is positioned adjacent to the gate structure. A portion of the source/drain feature embedded in the fin structure has an upper sidewall portion adjacent to a top surface of the fin structure and a lower sidewall portion below the upper sidewall portion. A first curve radius of the upper sidewall portion is different from a second curve radius of the lower sidewall portion in a cross-sectional view substantially along the longitudinal direction of the fin structure.

公开(公告)号：US20170179130A1

公开(公告)日：2017-06-22

申请号：US15446295

申请日：2017-03-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chang LIN ,  Chun-Feng NIEH ,  Huicheng CHANG ,  Hou-Yu CHEN ,  Yong-Yan LU

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7855

Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

公开(公告)号：US20240387188A1

公开(公告)日：2024-11-21

申请号：US18789319

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Fong TSAI ,  Ya-Lun CHEN ,  Tsai-Yu HUANG ,  Yahru CHENG ,  Huicheng CHANG ,  Yee-Chia YEO

IPC: H01L21/3105 ,  G03F7/16 ,  H01L21/027 ,  H01L21/311

Abstract: To reduce a thickness variation of a spin-on coating (SOC) layer that is applied over a plurality of first and second trenches with different pattern densities as a bottom layer in a photoresist stack, a two-step thermal treatment process is performed on the SOC layer. A first thermal treatment step in the two-step thermal treatment process is conducted at a first temperature below a cross-linking temperature of the SOC layer to cause flow of the SOC layer, and a second thermal treatment step in the two-step thermal treatment process is conducted at a second temperature to cause cross-linking of the SOC layer.

公开(公告)号：US20230386852A1

公开(公告)日：2023-11-30

申请号：US18446416

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Fong TSAI ,  Ya-Lun CHEN ,  Tsai-Yu HUANG ,  Yahru CHENG ,  Huicheng CHANG ,  Yee-Chia YEO

IPC: H01L21/3105 ,  G03F7/16 ,  H01L21/027 ,  H01L21/311

CPC classification number: H01L21/31058 ,  G03F7/168 ,  G03F7/162 ,  H01L21/0276 ,  H01L21/31144

Abstract: To reduce a thickness variation of a spin-on coating (SOC) layer that is applied over a plurality of first and second trenches with different pattern densities as a bottom layer in a photoresist stack, a two-step thermal treatment process is performed on the SOC layer. A first thermal treatment step in the two-step thermal treatment process is conducted at a first temperature below a cross-linking temperature of the SOC layer to cause flow of the SOC layer, and a second thermal treatment step in the two-step thermal treatment process is conducted at a second temperature to cause cross-linking of the SOC layer.