公开(公告)号：US09362338B2

公开(公告)日：2016-06-07

申请号：US14195636

申请日：2014-03-03

Applicant: SanDisk 3D LLC

Inventor： Naoki Takeguchi ,  Hiroaki Iuchi

IPC: H01L27/24 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/3213 ,  H01L27/10

CPC classification number: H01L27/2454 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823487 ,  H01L27/101 ,  H01L27/249 ,  H01L45/065 ,  H01L45/085 ,  H01L45/144 ,  H01L45/146 ,  H01L45/149

Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Each gate is formed over the gate dielectric and a base that extends horizontally at least partially between adjacent pillars. The base is formed with notches filled with the gate dielectric. The select device is fabricated using a conformally deposited base dielectric material and conformal hard mask layer that is formed with a larger bottom thickness than horizontal thickness. The base thickness is defined by the deposition thickness, rather than an uncontrolled etch back.

Abstract translation: 描述了具有垂直取向薄膜晶体管（TFT）选择器件和制造方法的三维（3D）非易失性存储器阵列。 垂直取向的TFT可以用作垂直位线选择装置，以将全局位线耦合到垂直位线。 选择器件柱包括主体和上部和下部源极/漏极区域。 至少一个栅极通过栅极电介质与选择器件柱水平分离。 每个栅极形成在栅极电介质上，并且基部至少部分地在相邻的柱之间水平延伸。 基座形成有填充有栅极电介质的凹口。 选择装置使用保形沉积的基底电介质材料和形成有比水平厚度更大的底部厚度的共形硬掩模层制造。 基底厚度由沉积厚度定义，而不是不受控制的回蚀。

公开(公告)号：US09356074B1

公开(公告)日：2016-05-31

申请号：US14543690

申请日：2014-11-17

Applicant: SanDisk 3D LLC

Inventor： Seiji Shimabukuro ,  Teruyuki Mine ,  Hiroyuki Ogawa ,  Naoki Takeguchi

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L27/249 ,  G11C5/025 ,  G11C7/18 ,  G11C8/12 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/025 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/35 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/148 ,  H01L45/149 ,  H01L45/16 ,  H01L45/1675

Abstract: A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.

Abstract translation: 非易失性数据存储设备包括由相应和垂直取向的位线选择器单元独立驱动的一对立即相邻和隔离的另一局部位线。 紧邻和隔离的另一局部位线之间的隔离也将非易失性数据存储设备的彼此各自的存储单元隔离，使得漏电流不能从连接到紧邻的第一个的存储器单元流出 并且与另一个本地位线隔离到连接到一对立即相邻和隔离的另一局部位线中的第二个的存储器单元。 编程期望的存储器单元的方法包括对与期望的存储单元的位线相邻的字线施加升压电压，而不对与该对的另一位线相邻的字线施加升压电压。

公开(公告)号：US20160141337A1

公开(公告)日：2016-05-19

申请号：US14543690

申请日：2014-11-17

Applicant: SanDisk 3D LLC

Inventor： Sejei Shimabukuro ,  Teruyuki Mine ,  Hiroyuki Ogawa ,  Naoki Takeguchi

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

CPC classification number: H01L27/249 ,  G11C5/025 ,  G11C7/18 ,  G11C8/12 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/025 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/35 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/148 ,  H01L45/149 ,  H01L45/16 ,  H01L45/1675

Abstract: A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.

Abstract translation: 非易失性数据存储设备包括由相应和垂直取向的位线选择器单元独立驱动的一对立即相邻和隔离的另一局部位线。 紧邻和隔离的另一局部位线之间的隔离也将非易失性数据存储设备的彼此各自的存储单元隔离，使得漏电流不能从连接到紧邻的第一个的存储器单元流出 并且与另一个本地位线隔离到连接到一对立即相邻和隔离的另一局部位线中的第二个的存储器单元。 编程期望的存储器单元的方法包括对与期望的存储单元的位线相邻的字线施加升压电压，而不对与该对的另一位线相邻的字线施加升压电压。

公开(公告)号：US20150249112A1

公开(公告)日：2015-09-03

申请号：US14195636

申请日：2014-03-03

Applicant: SanDisk 3D LLC

Inventor： Naoki Takeguchi ,  Hiroaki Iuchi

IPC: H01L27/24 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/8234

CPC classification number: H01L27/2454 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823487 ,  H01L27/101 ,  H01L27/249 ,  H01L45/065 ,  H01L45/085 ,  H01L45/144 ,  H01L45/146 ,  H01L45/149

Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Each gate is formed over the gate dielectric and a base that extends horizontally at least partially between adjacent pillars. The base is formed with notches that are filled with the gate dielectric. The select device is fabricated using a conformally deposited base dielectric material and conformal hard mask layer that is formed with a larger bottom thickness than horizontal thickness. The hard mask permits the base thickness to be defined by the deposition thickness, rather than an uncontrolled etch back.

Abstract translation: 描述了具有垂直取向薄膜晶体管（TFT）选择器件的三维（3D）非易失性存储器阵列及其制造方法。 垂直取向的TFT可以用作垂直位线选择装置，以将全局位线耦合到垂直位线。 选择器件柱包括主体和上部和下部源极/漏极区域。 至少一个栅极通过栅极电介质与选择器件柱水平分离。 每个栅极形成在栅极电介质上，并且基部至少部分地在相邻的柱之间水平延伸。 基座由填充有栅极电介质的凹口形成。 选择装置使用保形沉积的基底电介质材料和形成有比水平厚度更大的底部厚度的共形硬掩模层制造。 硬掩模允许基底厚度由沉积厚度定义，而不是不受控制的回蚀。