公开(公告)号：US20210110854A1

公开(公告)日：2021-04-15

申请号：US16746378

申请日：2020-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shubham RANJAN ,  Parvinder Kumar RANA ,  Janardhan ACHANTA ,  Manish Chandra JOSHI

IPC: G11C7/12 ,  G11C7/10

Abstract: Provided are apparatus and methods for compensating fabrication process variation of on-chip component(s) in shared memory bank. The method includes tracking a flip voltage level and tracking a discharge leakage current to disconnect a keeper circuit from the local read bit-line. The method includes controlling a read current and the discharge leakage current based on determining at least one of fast transistor and slow transistor associated with the at least one the keeper circuit and a bit-cell.

公开(公告)号：US20220103163A1

公开(公告)日：2022-03-31

申请号：US17175818

申请日：2021-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ankur GUPTA ,  Lava Kumar PULLURU ,  Parvinder Kumar RANA

IPC: H03K3/356 ,  H03K19/0185 ,  G11C11/412 ,  G11C11/419

Abstract: An apparatus includes a NMOS transistor having a drain, a first PMOS transistor having a drain connected to the drain of the NMOS transistor, a level shifter having an input and an output, the input of the level shifter being connected to the drain of the NMOS transistor and the drain of the first PMOS transistor, a first digital logic circuit having a drain and a gate, a first inverter having an input connected to the A output of the level shifter and the drain of the first digital logic circuit, and a second digital logic circuit having an output connected to the gate of the first digital logic circuit, at least one condition being set in the apparatus during a read operation.

公开(公告)号：US20200343267A1

公开(公告)日：2020-10-29

申请号：US16924377

申请日：2020-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shyam AGARWAL ,  Abhishek GHOSH ,  Parvinder Kumar RANA

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092

Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.

公开(公告)号：US20220028449A1

公开(公告)日：2022-01-27

申请号：US17443480

申请日：2021-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ankur GUPTA ,  Manish Chandra JOSHI ,  Parvinder Kumar RANA

IPC: G11C11/4093 ,  G11C11/408 ,  G11C11/4074 ,  G11C5/06 ,  G11C5/14

Abstract: The present invention discloses a wordline driver circuit for a random-access memory (RAM), which can reduce leakage during power down mode. The circuit includes a pre-driver stage on header and footer. The pre-driver stage includes a strap buffer defining a header and comprising a first switch connecting a first set of wordlines to a first voltage. The pre-driver stage includes an input-output buffer defining a footer and comprising a second switch connecting a second set of wordlines to a second voltage. In the pre-driver stage, the strap buffer further includes a third switch connecting the second set of wordlines to the first voltage and a fourth switch connecting the first set of wordlines to the second voltage.

公开(公告)号：US20200044631A1

公开(公告)日：2020-02-06

申请号：US16152931

申请日：2018-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shyam AGARWAL ,  Sandeep B V ,  Sheetal Y KOCHREKAR ,  Abhishek GHOSH ,  Parvinder Kumar RANA ,  Rohit BISHT

IPC: H03K3/3562 ,  H03K3/012

Abstract: A D flip-flop includes a master block configured to latch an input value of D at one of rising edge and a falling edge of a clock signal, based on the clock signal, the input value of D, and an inverted value of D, and a slave block configured to propagate the input value of D at another one of the falling edge and the rising edge of the clock signal, based on the clock signal.

公开(公告)号：US20180174657A1

公开(公告)日：2018-06-21

申请号：US15665988

申请日：2017-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Parvinder Kumar RANA ,  Lava Kumar PULLURU ,  Manish Chandra JOSHI

IPC: G11C16/32 ,  G11C16/08

CPC classification number: G11C16/32 ,  G11C7/222 ,  G11C8/12 ,  G11C16/08

Abstract: A system on-chip (SoC) device is provided. The SoC device includes an on-chip memory including memory banks, and internal clock generators. Each internal clock generator is coupled to one or more memory banks. Each internal clock generator generates one or more of an internal clock signal, a control signal and a clock reset signal locally for the memory bank to which the internal clock generator is coupled.

公开(公告)号：US20200075070A1

公开(公告)日：2020-03-05

申请号：US16166647

申请日：2018-10-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ankur GUPTA ,  Abhishek KESARWANI ,  Parvinder Kumar RANA ,  Manish Chandra JOSHI ,  Lava Kumar PULLURU

IPC: G11C8/10 ,  G11C7/22 ,  G11C8/06 ,  G11C8/08

Abstract: A fin-Field Effect Transistor based system on chip (SoC) memory is provided and includes a control block, first logic gates, and row decoder blocks. The control block includes a clock generator circuit that generates an internal clock signal, and a global driver circuit coupled to the clock generator circuit that drives a global clock signal. Each row decoder block includes a second logic gate that receives higher order non-clocked address signals via input terminals, a transmission gate that combines the global clock signal and the higher order non-clocked address signals, third logic gates that receive lower order non-clocked address signals and higher order clocked address signals, and output a combined lower order address and higher order address along with the global clock signal, level shifter circuits that receive the outputs, and word-line driver circuits that generate word-lines based on the output of the level shifter circuits.

公开(公告)号：US20190147944A1

公开(公告)日：2019-05-16

申请号：US16191717

申请日：2018-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： LAVA KUMAR PULLURU ,  Parvinder Kumar RANA ,  Akash Kumar GUPTA ,  Gayatri NAIR

IPC: G11C11/419 ,  G11C11/4097 ,  G11C7/10 ,  G11C8/12 ,  G11C7/12 ,  G11C7/18

CPC classification number: G11C11/419 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C8/12 ,  G11C11/4097 ,  G11C11/418 ,  G11C2207/005

Abstract: A static random-access memory (SRAM) system using a virtual banking architecture includes a processor communicatively coupled to an SRAM, and a plurality of circuits disposed in the SRAM and operated under control of the processor. The circuits include a divide circuit, a select circuit disposed in the divide circuit, and a local input/output circuit. The divide circuit divides a bank into first and second bit cell arrays, in which the first bit cell array and/or the second bit cell array includes at least one bit line. The select circuit is connected between the first and second bit cell arrays, and the select circuit selects one of the first and second bit cell arrays according to a predefined select logic. The local input/output circuit is connected to the select circuit and generates an output according to one or more predefined operations of the local input/output circuit.

公开(公告)号：US20190147943A1

公开(公告)日：2019-05-16

申请号：US16190278

申请日：2018-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Parvinder Kumar RANA ,  Lava Kumar PULLURU ,  Shuvadeep Kumar ,  Ankur GUPTA

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/08 ,  G11C7/222 ,  G11C8/08 ,  G11C8/18 ,  G11C11/418

Abstract: Embodiments herein provide a method for reducing power dissipation in a Static Random Access Memory (SRAM) device. The method includes determining, by the tracking circuit, whether at least one SRAM Bit-Cell discharges power from at least one BL exceeding a pre-defined voltage level required for a sense amplifier to perform a read operation. Furthermore, the method includes reducing, by the WL driver, the power discharged from the at least one BL by controlling a WL voltage power supply switch of the WL driver using a SAE signal and adjusting a pulse width of the at least one WL to pull down the at least one WL using a NMOS circuit when the at least one SRAM Bit-Cell discharges the power from the at least one BL exceeding the pre-defined voltage level.

公开(公告)号：US20180204607A1

公开(公告)日：2018-07-19

申请号：US15870013

申请日：2018-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Manish Chandra JOSHI ,  Parvinder Kumar RANA ,  Akash Kumar GUPTA

IPC: G11C7/18 ,  G11C7/10

CPC classification number: G11C7/18 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/14

Abstract: A memory for providing a signal buffering scheme for array and periphery signals and the operating method of the same are provided. The memory includes a plurality of columns of memory cells, a control circuit, and a control logic unit. The plurality of columns of memory cells may be connected to a local array signal generator via local control lines, which are connected to a global array signal generator via global control lines for receiving array signals. The control circuit may be connected to the memory cells for providing periphery signals. The control logic unit may be connected to the memory cells through a hierarchical structure of the global control lines and the local control lines. The control logic unit may be configured to provide the array signals and periphery signals having the same polarity to the global control lines and the local control lines.