公开(公告)号：US20190147944A1

公开(公告)日：2019-05-16

申请号：US16191717

申请日：2018-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： LAVA KUMAR PULLURU ,  Parvinder Kumar RANA ,  Akash Kumar GUPTA ,  Gayatri NAIR

IPC: G11C11/419 ,  G11C11/4097 ,  G11C7/10 ,  G11C8/12 ,  G11C7/12 ,  G11C7/18

CPC classification number: G11C11/419 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C8/12 ,  G11C11/4097 ,  G11C11/418 ,  G11C2207/005

Abstract: A static random-access memory (SRAM) system using a virtual banking architecture includes a processor communicatively coupled to an SRAM, and a plurality of circuits disposed in the SRAM and operated under control of the processor. The circuits include a divide circuit, a select circuit disposed in the divide circuit, and a local input/output circuit. The divide circuit divides a bank into first and second bit cell arrays, in which the first bit cell array and/or the second bit cell array includes at least one bit line. The select circuit is connected between the first and second bit cell arrays, and the select circuit selects one of the first and second bit cell arrays according to a predefined select logic. The local input/output circuit is connected to the select circuit and generates an output according to one or more predefined operations of the local input/output circuit.

公开(公告)号：US20200251164A1

公开(公告)日：2020-08-06

申请号：US16857269

申请日：2020-04-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： LAVA KUMAR PULLURU ,  PARVINDER KUMAR RANA ,  AKASH KUMAR GUPTA ,  GAYATRI NAIR

IPC: G11C11/419 ,  G11C11/4097 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  G11C8/12 ,  G11C11/418

Abstract: A static random-access memory (SRAM) system using a virtual banking architecture includes a processor communicatively coupled to an SRAM, and a plurality of circuits disposed in the SRAM and operated under control of the processor. The circuits include a divide circuit, a select circuit disposed in the divide circuit, and a local input/output circuit. The divide circuit divides a bank into first and second bit cell arrays, in which the first bit cell array and/or the second bit cell array includes at least one bit line. The select circuit is connected between the first and second bit cell arrays, and the select circuit selects one of the first and second bit cell arrays according to a predefined select logic. The local input/output circuit is connected to the select circuit and generates an output according to one or more predefined operations of the local input/output circuit.