公开(公告)号：US20210110854A1

公开(公告)日：2021-04-15

申请号：US16746378

申请日：2020-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shubham RANJAN ,  Parvinder Kumar RANA ,  Janardhan ACHANTA ,  Manish Chandra JOSHI

IPC: G11C7/12 ,  G11C7/10

Abstract: Provided are apparatus and methods for compensating fabrication process variation of on-chip component(s) in shared memory bank. The method includes tracking a flip voltage level and tracking a discharge leakage current to disconnect a keeper circuit from the local read bit-line. The method includes controlling a read current and the discharge leakage current based on determining at least one of fast transistor and slow transistor associated with the at least one the keeper circuit and a bit-cell.

公开(公告)号：US20220028449A1

公开(公告)日：2022-01-27

申请号：US17443480

申请日：2021-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ankur GUPTA ,  Manish Chandra JOSHI ,  Parvinder Kumar RANA

IPC: G11C11/4093 ,  G11C11/408 ,  G11C11/4074 ,  G11C5/06 ,  G11C5/14

Abstract: The present invention discloses a wordline driver circuit for a random-access memory (RAM), which can reduce leakage during power down mode. The circuit includes a pre-driver stage on header and footer. The pre-driver stage includes a strap buffer defining a header and comprising a first switch connecting a first set of wordlines to a first voltage. The pre-driver stage includes an input-output buffer defining a footer and comprising a second switch connecting a second set of wordlines to a second voltage. In the pre-driver stage, the strap buffer further includes a third switch connecting the second set of wordlines to the first voltage and a fourth switch connecting the first set of wordlines to the second voltage.

公开(公告)号：US20180174657A1

公开(公告)日：2018-06-21

申请号：US15665988

申请日：2017-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Parvinder Kumar RANA ,  Lava Kumar PULLURU ,  Manish Chandra JOSHI

IPC: G11C16/32 ,  G11C16/08

CPC classification number: G11C16/32 ,  G11C7/222 ,  G11C8/12 ,  G11C16/08

Abstract: A system on-chip (SoC) device is provided. The SoC device includes an on-chip memory including memory banks, and internal clock generators. Each internal clock generator is coupled to one or more memory banks. Each internal clock generator generates one or more of an internal clock signal, a control signal and a clock reset signal locally for the memory bank to which the internal clock generator is coupled.

公开(公告)号：US20240161821A1

公开(公告)日：2024-05-16

申请号：US18163584

申请日：2023-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Poornima VENKATASUBRAMANIAN ,  Pushp KHATTER ,  Lava Kumar PULLURU ,  Manish Chandra JOSHI ,  Ved PRAKASH ,  Anurag KUMAR ,  Surendra DESHMUKH

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: A write assist circuit includes a first power control circuit and second power control circuit, each comprising a first switch and second switch. The first switch of first power control circuit has first drive strength and is configured to be controlled by a column select line, a power control line, a first bit line, and a power supply. The first switch of the second power control circuit has the first drive strength and is configured to be controlled by the column select line, the power control line, a second bit line, and the power supply. The second switch has a second drive strength and is configured to be controlled by the power control line. The first switches are configured to be controlled using input data on first- and second-bit line, respectively, for altering power supply to first inverter and second inverter of SRAM bitcell.

公开(公告)号：US20230282251A1

公开(公告)日：2023-09-07

申请号：US17750690

申请日：2022-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Lava Kumar PULLURU ,  Poornima VENKATASUBRAMANIAN ,  Manish Chandra JOSHI ,  Ved PRAKASH ,  Pushp KHATTER

IPC: G11C7/10 ,  H03K3/037

CPC classification number: G11C7/1039 ,  G11C7/1066 ,  G11C7/1093 ,  H03K3/0372

Abstract: A memory device includes at least one bitcell; read circuitry coupled to the at least one bitcell; and screening circuitry coupled to the read circuitry, wherein the screening circuitry includes a master slave flip-flop configured to store an output of the at least one bitcell during a read operation of the memory device, wherein the master slave flip-flop includes a master latch and a slave latch; and a DOUT window controller coupled to the master slave flip-flop and configured to generate and control a master clock signal for the master latch to determine if the at least one bitcell is a weak bitcell; and generate and control a slave clock signal for the slave latch to enable toggling of the output of the at least one bitcell during a transparent window between the master clock signal and the slave clock signal.

公开(公告)号：US20200075070A1

公开(公告)日：2020-03-05

申请号：US16166647

申请日：2018-10-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ankur GUPTA ,  Abhishek KESARWANI ,  Parvinder Kumar RANA ,  Manish Chandra JOSHI ,  Lava Kumar PULLURU

IPC: G11C8/10 ,  G11C7/22 ,  G11C8/06 ,  G11C8/08

Abstract: A fin-Field Effect Transistor based system on chip (SoC) memory is provided and includes a control block, first logic gates, and row decoder blocks. The control block includes a clock generator circuit that generates an internal clock signal, and a global driver circuit coupled to the clock generator circuit that drives a global clock signal. Each row decoder block includes a second logic gate that receives higher order non-clocked address signals via input terminals, a transmission gate that combines the global clock signal and the higher order non-clocked address signals, third logic gates that receive lower order non-clocked address signals and higher order clocked address signals, and output a combined lower order address and higher order address along with the global clock signal, level shifter circuits that receive the outputs, and word-line driver circuits that generate word-lines based on the output of the level shifter circuits.

公开(公告)号：US20180204607A1

公开(公告)日：2018-07-19

申请号：US15870013

申请日：2018-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Manish Chandra JOSHI ,  Parvinder Kumar RANA ,  Akash Kumar GUPTA

IPC: G11C7/18 ,  G11C7/10

CPC classification number: G11C7/18 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/14

Abstract: A memory for providing a signal buffering scheme for array and periphery signals and the operating method of the same are provided. The memory includes a plurality of columns of memory cells, a control circuit, and a control logic unit. The plurality of columns of memory cells may be connected to a local array signal generator via local control lines, which are connected to a global array signal generator via global control lines for receiving array signals. The control circuit may be connected to the memory cells for providing periphery signals. The control logic unit may be connected to the memory cells through a hierarchical structure of the global control lines and the local control lines. The control logic unit may be configured to provide the array signals and periphery signals having the same polarity to the global control lines and the local control lines.