公开(公告)号：US20230395662A1

公开(公告)日：2023-12-07

申请号：US18299086

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seojin Jeong ,  Jungtaek Kim ,  Moonseung Yang ,  Sumin Yu ,  Namkyu Cho ,  Seokhoon Kim ,  Pankwi Park

IPC: H01L29/08 ,  H01L29/775 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L29/775 ,  H01L29/42392 ,  H01L29/0673

Abstract: Semiconductor device may include an active region extending in a first direction, channel layers spaced apart from each other in a vertical direction, a gate structure extending on the active region and the channel layers to surround the channel layers and extending in a second direction, and a source/drain region on the active region adjacent to a side of the gate structure and contacting the plurality of channel layers. The source/drain region includes first to sixth epitaxial layers that are sequentially stacked in the vertical direction and have respective first to sixth germanium (Ge) concentrations. The first Ge concentration is lower than the second Ge concentration, the third Ge concentration is lower than the second Ge concentration and the fourth Ge concentration, and the fifth Ge concentration is lower than the fourth Ge concentration and the sixth Ge concentration.

公开(公告)号：US11888026B2

公开(公告)日：2024-01-30

申请号：US17467944

申请日：2021-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Choi ,  Seojin Jeong ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Moonseung Yang ,  Ryong Ha

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/0665 ,  H01L29/6656 ,  H01L29/78618

Abstract: An integrated circuit device includes a fin-type active region on a substrate; at least one nanosheet having a bottom surface facing the fin top; a gate line on the fin-type active region; and a source/drain region on the fin-type active region, adjacent to the gate line, and in contact with the at least one nanosheet, wherein the source/drain region includes a lower main body layer and an upper main body layer, a top surface of the lower main body layer includes a lower facet declining toward the substrate as it extends in a direction from the at least one nanosheet to a center of the source/drain region, and the upper main body layer includes a bottom surface contacting the lower facet and a top surface having an upper facet. With respect to a vertical cross section, the lower facet extends along a corresponding first line and the upper facet extends along a second line that intersects the first line.

公开(公告)号：US11183562B2

公开(公告)日：2021-11-23

申请号：US16750273

申请日：2020-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihye Yi ,  Moonseung Yang ,  Jungtaek Kim

IPC: H01L29/423 ,  H01L29/10 ,  H01L29/417 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/265

Abstract: A semiconductor device includes a substrate including an active region in a first direction, a plurality of channel layers on the active region and disposed in a direction perpendicular to an upper surface of the substrate, a gate electrode respectively surrounding the plurality of channel layers, and a source/drain structure respectively disposed on both sides of the gate electrode in the first direction and connected to each of the plurality of channel layers. The gate electrode extends in a second direction crossing the first direction. The gate electrode includes an overlapped portion in a region of the gate electrode on an uppermost channel layer of the plurality of channel layers. The overlapped portion of the gate electrode overlaps the source/drain structure in the first direction and has a side surface inclined toward the upper surface of the substrate.

公开(公告)号：US20220190109A1

公开(公告)日：2022-06-16

申请号：US17467944

申请日：2021-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Choi ,  Seojin Jeong ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Moonseung Yang ,  Ryong Ha

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/66

Abstract: An integrated circuit device includes a fin-type active region on a substrate; at least one nanosheet having a bottom surface facing the fin top; a gate line on the fin-type active region; and a source/drain region on the fin-type active region, adjacent to the gate line, and in contact with the at least one nanosheet, wherein the source/drain region includes a lower main body layer and an upper main body layer, a top surface of the lower main body layer includes a lower facet declining toward the substrate as it extends in a direction from the at least one nanosheet to a center of the source/drain region, and the upper main body layer includes a bottom surface contacting the lower facet and a top surface having an upper facet. With respect to a vertical cross section, the lower facet extends along a corresponding first line and the upper facet extends along a second line that intersects the first line.

公开(公告)号：US11264381B2

公开(公告)日：2022-03-01

申请号：US16841806

申请日：2020-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungryul Lee ,  Yongseung Kim ,  Jungtaek Kim ,  Pankwi Park ,  Dongchan Suh ,  Moonseung Yang ,  Seojin Jeong ,  Minhee Choi ,  Ryong Ha

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

Abstract: An integrated circuit device includes a fin-type active region protruding from a substrate and extending in a first direction, a plurality of semiconductor patterns disposed apart from an upper surface of the fin-type active region, the plurality of semiconductor patterns each including a channel region; a gate electrode surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, and including a main gate electrode, which is disposed on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and a sub-gate electrode disposed between the plurality of semiconductor patterns; a spacer structure disposed on both sidewalls of the main gate electrode; and a source/drain region connected to the plurality of semiconductor patterns, disposed at both sides of the gate electrode, and contacting a bottom surface of the spacer structure.

公开(公告)号：US20240096945A1

公开(公告)日：2024-03-21

申请号：US18527453

申请日：2023-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Choi ,  Seojin Jeong ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Moonseung Yang ,  Ryong Ha

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L29/6656 ,  H01L29/78618

Abstract: An integrated circuit device includes a fin-type active region on a substrate; at least one nanosheet having a bottom surface facing the fin top; a gate line on the fin-type active region; and a source/drain region on the fin-type active region, adjacent to the gate line, and in contact with the at least one nanosheet, wherein the source/drain region includes a lower main body layer and an upper main body layer, a top surface of the lower main body layer includes a lower facet declining toward the substrate as it extends in a direction from the at least one nanosheet to a center of the source/drain region, and the upper main body layer includes a bottom surface contacting the lower facet and a top surface having an upper facet. With respect to a vertical cross section, the lower facet extends along a corresponding first line and the upper facet extends along a second line that intersects the first line.

公开(公告)号：US20240030286A1

公开(公告)日：2024-01-25

申请号：US18140905

申请日：2023-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Heo ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Moonseung Yang ,  Sumin Yu ,  Seojin Jeong ,  Edward Namkyu Cho ,  Ryong Ha

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/02532 ,  H01L29/66545 ,  H01L29/66439

Abstract: An integrated circuit device includes a plurality of fin-type active areas extending in a first horizontal direction on a substrate, a plurality of channel regions respectively on the plurality of fin-type active areas, a plurality of gate lines surrounding the plurality of channel regions on the plurality of fin-type active areas and extending in a second horizontal direction that crosses the first horizontal direction, and a plurality of source/drain regions respectively at positions adjacent to the plurality of gate lines on the plurality of fin-type active areas and respectively in contact with the plurality of channel regions, and the plurality of source/drain regions respectively include a plurality of semiconductor layers and at least one air gap located therein.

公开(公告)号：US11862682B2

公开(公告)日：2024-01-02

申请号：US17511778

申请日：2021-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihye Yi ,  Moonseung Yang ,  Jungtaek Kim

IPC: H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/265

CPC classification number: H01L29/1037 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/26513 ,  H01L21/308 ,  H01L21/30604 ,  H01L21/31116 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate including an active region in a first direction, a plurality of channel layers on the active region and disposed in a direction perpendicular to an upper surface of the substrate, a gate electrode respectively surrounding the plurality of channel layers, and a source/drain structure respectively disposed on both sides of the gate electrode in the first direction and connected to each of the plurality of channel layers. The gate electrode extends in a second direction crossing the first direction. The gate electrode includes an overlapped portion in a region of the gate electrode on an uppermost channel layer of the plurality of channel layers. The overlapped portion of the gate electrode overlaps the source/drain structure in the first direction and has a side surface inclined toward the upper surface of the substrate.

公开(公告)号：US20230402459A1

公开(公告)日：2023-12-14

申请号：US18185941

申请日：2023-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seojin Jeong ,  Jungtaek Kim ,  Moonseung Yang ,  Sumin Yu ,  Edward Namkyu Cho ,  Seokhoon Kim ,  Pankwi Park

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H01L29/423

CPC classification number: H01L27/0924 ,  H01L29/7851 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/42392

Abstract: An integrated circuit (IC) device includes a fin-type active region, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region, a source/drain region that is adjacent to the gate line on the fin-type active region and has a sidewall facing the channel region, wherein the source/drain region includes a first buffer layer, a second buffer layer, and a main body layer, which are sequentially stacked in a direction away from the fin-type active region, each include a Si1-xGex layer (x≠0) doped with a p-type dopant, and have different Ge concentrations, and the second buffer layer conformally covers a surface of the first buffer layer that faces the main body layer. A thickness ratio of the side buffer portion to the bottom buffer portion is in a range of about 0.9 to about 1.1.

公开(公告)号：US20230378336A1

公开(公告)日：2023-11-23

申请号：US18117405

申请日：2023-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namkyu Cho ,  Jungtaek Kim ,  Moonseung Yang ,  Sumin Yu ,  Seojin Jeong ,  Seokhoon Kim ,  Pankwi Park

IPC: H01L29/775 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/775 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/0649 ,  H01L29/41775

Abstract: A semiconductor device includes an active region extending on a substrate in a first direction, a plurality of channel layers on the active region to be spaced apart from each other in a vertical direction, perpendicular to an upper surface of the substrate, the plurality of channel layers including silicon germanium, a gate structure intersecting the active region and the plurality of channel layers on the substrate to surround the plurality of channel layers, respectively, a source/drain region on the active region on at least one side of the gate structure, the source/drain region in contact with the plurality of channel layers, and a substrate insulating layer disposed between the source/drain region and the substrate. The source/drain region includes a first layer in contact with a side surface of the gate structure, side surfaces of the plurality of channel layers, and an upper surface of the substrate insulating layer.