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    Nonvolatile memory devices and methods of forming same
    1.
    发明授权
    Nonvolatile memory devices and methods of forming same 有权

    公开(公告)号：US09704878B2

    公开(公告)日：2017-07-11

    申请号：US15252931

    申请日：2016-08-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Woong-Seop Lee ,  Seokcheon Baek ,  Jinhyun Shin

    IPC: H01L21/70 ,  H01L27/11582 ,  H01L27/11556

    CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11575

    Abstract: A vertical NAND-type memory device includes a vertical stack of inter-gate insulating layers and gate electrodes arranged in an alternating sequence on an underlying substrate, which includes a cell array region and a contact region therein. At least one NAND-type channel structure is provided, which extends vertically through the vertical stack of inter-gate insulating layers and gate electrodes. An end sidewall of a first of the gate electrodes, which extends laterally over at least a portion of the contact region, has a vertical slope that is less steep than vertical slopes of end sidewalls of a first plurality of the gate electrodes extending between the first of the gate electrodes and the substrate.

    NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING SAME
    2.
    发明申请
    NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING SAME 审中-公开

    公开(公告)号：US20170301688A1

    公开(公告)日：2017-10-19

    申请号：US15613602

    申请日：2017-06-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Woong-Seop Lee ,  Seokcheon Baek ,  Jinhyun Shin

    IPC: H01L27/115

    CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11575

    Abstract: A vertical NAND-type memory device includes a vertical stack of inter-gate insulating layers and gate electrodes arranged in an alternating sequence on an underlying substrate, which includes a cell array region and a contact region therein. At least one NAND-type channel structure is provided, which extends vertically through the vertical stack of inter-gate insulating layers and gate electrodes. An end sidewall of a first of the gate electrodes, which extends laterally over at least a portion of the contact region, has a vertical slope that is less steep than vertical slopes of end sidewalls of a first plurality of the gate electrodes extending between the first of the gate electrodes and the substrate.

    Semiconductor memory devices and methods of fabricating the same
    6.
    发明授权
    Semiconductor memory devices and methods of fabricating the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US09379123B2

    公开(公告)日：2016-06-28

    申请号：US14848423

    申请日：2015-09-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Hwang Sim ,  Jinhyun Shin ,  Jong-Min Lee

    IPC: H01L21/764 ,  H01L27/115 ,  H01L29/423

    CPC classification number: H01L27/11524 ,  H01L21/764 ,  H01L29/42324

    Abstract: Provided are a semiconductor memory device and a method of fabricating the same. the semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench.

    Abstract translation: 提供一种半导体存储器件及其制造方法。 半导体存储器件可以包括半导体衬底，其具有限定第一区域中的有源区域的第一沟槽和设置在第一区域周围的第二区域中的第二沟槽，设置在第一区域上的栅电极以跨越有源区域， 存储图案，设置在所述栅电极和所述有源区之间，阻挡绝缘层，设置在所述栅电极和所述电荷存储图案之间并在所述第一沟槽上延伸以限定所述第一沟槽中的第一气隙，以及间隔开的绝缘图案 从第二沟槽的底表面到第二沟槽中限定第二气隙。

    Methods of fabricating semiconductor devices and devices fabricated thereby
    7.
    发明授权
    Methods of fabricating semiconductor devices and devices fabricated thereby 有权
    制造半导体器件的方法和由此制造的器件

    公开(公告)号：US09378979B2

    公开(公告)日：2016-06-28

    申请号：US14503498

    申请日：2014-10-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Hwang Sim ,  Jinhyun Shin

    IPC: H01L21/302 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/311 ,  H01L27/115

    CPC classification number: H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L27/11519 ,  H01L27/11531

    Abstract: Methods of fabricating semiconductor devices are provided including performing two photolithography processes and two spacer processes such that patterns are formed to have a pitch that is smaller than a limitation of photolithography process. Furthermore, line and pad portions are simultaneously defined by performing the photolithography process once and, thus, there is no necessity to perform an additional photolithography process for forming the pad portion. Related devices are also provided.

    Abstract translation: 提供制造半导体器件的方法包括执行两个光刻工艺和两个间隔工艺，使得图案形成为具有小于光刻工艺限制的间距。 此外，通过执行一次光刻工艺同时限定线和焊盘部分，因此不需要执行用于形成焊盘部分的附加光刻工艺。 还提供了相关设备。

    Three-dimensional semiconductor memory device
    8.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US10128266B2

    公开(公告)日：2018-11-13

    申请号：US15592030

    申请日：2017-05-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jung Hoon Lee ,  Keejeong Rho ,  Sejun Park ,  Jinhyun Shin ,  Dong-Sik Lee ,  Woong-Seop Lee

    IPC: H01L27/11582 ,  H01L23/528 ,  G11C16/08 ,  H01L27/11556 ,  H01L27/1157

    Abstract: A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances.

    NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING SAME
    10.
    发明申请
    NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING SAME 有权

    公开(公告)号：US20170103996A1

    公开(公告)日：2017-04-13

    申请号：US15252931

    申请日：2016-08-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Woong-Seop Lee ,  Seokcheon Baek ,  Jinhyun Shin

    IPC: H01L27/115

    CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11575

    Abstract: A vertical NAND-type memory device includes a vertical stack of inter-gate insulating layers and gate electrodes arranged in an alternating sequence on an underlying substrate, which includes a cell array region and a contact region therein. At least one NAND-type channel structure is provided, which extends vertically through the vertical stack of inter-gate insulating layers and gate electrodes. An end sidewall of a first of the gate electrodes, which extends laterally over at least a portion of the contact region, has a vertical slope that is less steep than vertical slopes of end sidewalls of a first plurality of the gate electrodes extending between the first of the gate electrodes and the substrate.

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