公开(公告)号：US10128266B2

公开(公告)日：2018-11-13

申请号：US15592030

申请日：2017-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Hoon Lee ,  Keejeong Rho ,  Sejun Park ,  Jinhyun Shin ,  Dong-Sik Lee ,  Woong-Seop Lee

IPC: H01L27/11582 ,  H01L23/528 ,  G11C16/08 ,  H01L27/11556 ,  H01L27/1157

Abstract: A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances.

公开(公告)号：US10700088B2

公开(公告)日：2020-06-30

申请号：US16220836

申请日：2018-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongwon Kim ,  Keejeong Rho ,  Jin-Yeon Won ,  Tae-Wan Lim ,  Woohyun Park

IPC: H01L27/11582 ,  H01L27/11565

Abstract: Semiconductor memory devices and methods for manufacturing the same are provided. The device may include vertical channel structures that are two-dimensionally arranged on a substrate and vertically extend from the substrate. The device may also include bit lines on the vertical channel structures, and each of the bit lines may be commonly connected to the vertical channel structures arranged in a first direction. The device may further include common source lines that extend between the vertical channel structures in a second direction intersecting the first direction and a source strapping line that is disposed at the same vertical level as the bit lines and electrically connects the common source lines to each other.

公开(公告)号：US20190139984A1

公开(公告)日：2019-05-09

申请号：US16220836

申请日：2018-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongwon KIM ,  Keejeong Rho ,  Jin-Yeon Won ,  Tae-Wan Lim ,  Woohyun Park

IPC: H01L27/11582 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/11565

Abstract: Semiconductor memory devices and methods for manufacturing the same are provided. The device may include vertical channel structures that are two-dimensionally arranged on a substrate and vertically extend from the substrate. The device may also include bit lines on the vertical channel structures, and each of the bit lines may be commonly connected to the vertical channel structures arranged in a first direction. The device may further include common source lines that extend between the vertical channel structures in a second direction intersecting the first direction and a source strapping line that is disposed at the same vertical level as the bit lines and electrically connects the common source lines to each other.

公开(公告)号：US09659958B2

公开(公告)日：2017-05-23

申请号：US15291521

申请日：2016-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Hoon Lee ,  Keejeong Rho ,  Sejun Park ,  Jinhyun Shin ,  Dong-Sik Lee ,  Woong-Seop Lee

IPC: H01L27/115 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  G11C16/08 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/1157

Abstract: A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances.