公开(公告)号：US20250048628A1

公开(公告)日：2025-02-06

申请号：US18437604

申请日：2024-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JOONYOUNG KWON ,  JIYOUNG KIM ,  JUNHYOUNG KIM ,  SUKKANG SUNG

IPC: H10B43/27 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: The present disclosure relates to three-dimensional (3D) semiconductor memory devices and electronic systems. An example 3D semiconductor memory device comprises a peripheral circuit structure on a peripheral substrate, a stack structure that includes a plurality of gate electrodes stacked on the peripheral circuit structure, an n-doped pattern on the stack structure, a vertical structure that extends through the stack structure into the n-doped pattern, a p-doped pattern on the n-doped pattern, and an undoped pattern between the n-doped pattern and then p-doped pattern. The p-doped pattern includes a p-doped horizontal pattern on the undoped pattern, and a p-doped vertical pattern that extends through the undoped pattern and the n-doped pattern and that contacts with the vertical structure.

公开(公告)号：US20200066742A1

公开(公告)日：2020-02-27

申请号：US16398442

申请日：2019-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNHYOUNG KIM ,  KWANG-SOO KIM ,  GEUNWON LIM ,  JISUNG CHEON

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device may include a first stack block including first stacks arranged in a first direction on a substrate, a second stack block including second stacks arranged in the first direction on the substrate, and a separation structure provided on the substrate between the first stack block and the second stack block. The separation structure may include first mold layers and second mold layers, which are stacked in a vertical direction perpendicular to a top surface of the substrate.

公开(公告)号：US20240405091A1

公开(公告)日：2024-12-05

申请号：US18541229

申请日：2023-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNHYOUNG KIM ,  Joonyoung KWON ,  Jiyoung KIM ,  Sukkang SUNG

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/768

Abstract: A semiconductor device includes a gate stacking structure including alternating gate electrodes and insulation layers on an insulation portion, a channel structure crossing the insulation portion and extending through the gate stacking structure, and a horizontal conductive layer connected to the channel structure between the insulation portion and the gate stacking structure, the horizontal conductive layer including a doped monocrystalline semiconductor layer having a dopant.

公开(公告)号：US20240237340A1

公开(公告)日：2024-07-11

申请号：US18219697

申请日：2023-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIWON KIM ,  Ahreum Lee ,  JOONYOUNG KWON ,  Dohyung Kim ,  JUNHYOUNG KIM ,  SUKKANG SUNG

IPC: H10B43/27 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H01L25/0655 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device includes a cell region in which a channel structure is disposed and memory cells arranged in three dimensions are disposed, a cell contact region in which a cell contact plug is disposed, a common source line contact region in which a common source line contact plug is disposed, an input and output contact region in which an input and output contact plug is disposed, a word line cut region separating word lines of the cell region from word lines of a neighboring cell region, a common source line layer connecting the channel structure and the common source line contact plug, and an input and output pad connected to the input and output contact plug. The common source line layer and the input and output pad are disposed at the same vertical level.

公开(公告)号：US20230354604A1

公开(公告)日：2023-11-02

申请号：US18072312

申请日：2022-11-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGMIN LEE ,  JUNHYOUNG KIM ,  YOUNGBUM WOO ,  JOONSUNG LIM

IPC: H10B43/27 ,  H10B41/10 ,  H01L23/522 ,  H01L23/528 ,  H10B41/35 ,  H10B41/27 ,  H10B43/35 ,  H10B43/10

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565

Abstract: A semiconductor device includes a first semiconductor structure including a first substrate, circuit devices disposed on the first substrate, and first metal bonding layers disposed on the circuit devices, and a second semiconductor structure including gate electrodes spaced apart from each other and stacked in a first direction, perpendicular to upper surfaces of the first metal bonding layers, channel structures passing through the gate electrodes, extending in the first direction, and respectively including a channel layer, second metal bonding layers disposed below the channel structures and the gate electrodes and connected to the first metal bonding layers, bit lines disposed below the channel structures, extending in a second direction, perpendicular to the first direction, and spaced apart from each other, and source lines disposed on the channel structures, extending in a third direction, perpendicular to the second direction, and spaced apart from each other. The channel structures are respectively disposed in intersection regions in which the bit lines and the source lines intersect each other.

公开(公告)号：US20210305271A1

公开(公告)日：2021-09-30

申请号：US17032128

申请日：2020-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNHYOUNG KIM ,  JISUNG CHEON ,  YOONHWAN SON ,  SEUNGMIN LEE

IPC: H01L27/11578 ,  H01L27/11573 ,  H01L27/11568

Abstract: A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.

公开(公告)号：US20250151279A1

公开(公告)日：2025-05-08

申请号：US18668971

申请日：2024-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNHYOUNG KIM ,  JIYOUNG KIM ,  IK-HYUNG JOO ,  SUKKANG SUNG ,  SEHOON LEE

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A semiconductor device includes a semiconductor substrate, and a first transistor disposed on the semiconductor substrate. The first transistor includes an insulation structure disposed on the semiconductor substrate, a channel region disposed on the insulation structure and including a first semiconductor layer, and extending in a direction crossing the semiconductor substrate, first source and drain regions electrically connected to the channel region, a first gate insulating layer disposed on the channel region, and a first gate electrode disposed on the first gate insulating layer. A first region that is one of the first source and drain regions and a second region that is another one of the first source and drain regions include different materials or have different crystal structures.

公开(公告)号：US20220415919A1

公开(公告)日：2022-12-29

申请号：US17897255

申请日：2022-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNHYOUNG KIM ,  JISUNG CHEON ,  YOONHWAN SON ,  SEUNGMIN LEE

IPC: H01L27/11578 ,  H01L27/11568 ,  H01L27/11573

Abstract: A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.

公开(公告)号：US20220173028A1

公开(公告)日：2022-06-02

申请号：US17509713

申请日：2021-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNHYOUNG KIM

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device includes a plurality of gate electrodes on a substrate to be spaced apart from each other in a vertical direction; a plurality of channel structures penetrating through the gate electrodes and extending in the vertical direction; a string separation insulation layer penetrating through two topmost gate electrodes and extending in a first horizontal direction; a plurality of bit line contacts on the plurality of channel structures; and a plurality of bit lines on the plurality of bit line contacts. Each of the bit lines includes a first segment extending in a second horizontal direction; a second segment spaced apart from the first segment in the first horizontal direction and extending in the second horizontal direction; and a first bending portion connecting the first segment to the second segment and extending at inclination angle of about 20 to 70 degrees with respect to the second horizontal direction.