公开(公告)号：US20250048628A1

公开(公告)日：2025-02-06

申请号：US18437604

申请日：2024-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JOONYOUNG KWON ,  JIYOUNG KIM ,  JUNHYOUNG KIM ,  SUKKANG SUNG

IPC: H10B43/27 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: The present disclosure relates to three-dimensional (3D) semiconductor memory devices and electronic systems. An example 3D semiconductor memory device comprises a peripheral circuit structure on a peripheral substrate, a stack structure that includes a plurality of gate electrodes stacked on the peripheral circuit structure, an n-doped pattern on the stack structure, a vertical structure that extends through the stack structure into the n-doped pattern, a p-doped pattern on the n-doped pattern, and an undoped pattern between the n-doped pattern and then p-doped pattern. The p-doped pattern includes a p-doped horizontal pattern on the undoped pattern, and a p-doped vertical pattern that extends through the undoped pattern and the n-doped pattern and that contacts with the vertical structure.

公开(公告)号：US20240237340A1

公开(公告)日：2024-07-11

申请号：US18219697

申请日：2023-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIWON KIM ,  Ahreum Lee ,  JOONYOUNG KWON ,  Dohyung Kim ,  JUNHYOUNG KIM ,  SUKKANG SUNG

IPC: H10B43/27 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H01L25/0655 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device includes a cell region in which a channel structure is disposed and memory cells arranged in three dimensions are disposed, a cell contact region in which a cell contact plug is disposed, a common source line contact region in which a common source line contact plug is disposed, an input and output contact region in which an input and output contact plug is disposed, a word line cut region separating word lines of the cell region from word lines of a neighboring cell region, a common source line layer connecting the channel structure and the common source line contact plug, and an input and output pad connected to the input and output contact plug. The common source line layer and the input and output pad are disposed at the same vertical level.