公开(公告)号：US20240237340A1

公开(公告)日：2024-07-11

申请号：US18219697

申请日：2023-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIWON KIM ,  Ahreum Lee ,  JOONYOUNG KWON ,  Dohyung Kim ,  JUNHYOUNG KIM ,  SUKKANG SUNG

IPC: H10B43/27 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H01L25/0655 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device includes a cell region in which a channel structure is disposed and memory cells arranged in three dimensions are disposed, a cell contact region in which a cell contact plug is disposed, a common source line contact region in which a common source line contact plug is disposed, an input and output contact region in which an input and output contact plug is disposed, a word line cut region separating word lines of the cell region from word lines of a neighboring cell region, a common source line layer connecting the channel structure and the common source line contact plug, and an input and output pad connected to the input and output contact plug. The common source line layer and the input and output pad are disposed at the same vertical level.

公开(公告)号：US20240074173A1

公开(公告)日：2024-02-29

申请号：US18300022

申请日：2023-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahreum Lee ,  Woosung Yang ,  Jimo Gu ,  Jaeho Kim ,  Sukkang Sung

IPC: H10B41/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B41/27 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: According to some embodiments of inventive concepts, vertical nonvolatile memory devices and related methods may reduce chip size. The nonvolatile memory device may include a substrate wherein a first direction is orthogonal with respect to a surface of the substrate and wherein the substrate includes a cell array area and an extension area. A first gate structure layer on the substrate may include a plurality of first gate layers. A contact separation layer may be on the first gate structure layer on the extension area. A second gate structure layer on the first gate structure layer and on the contact separation layer may include a plurality of second gate layers. A plurality of channel structures may extend in the first direction through the first and second gate structure layers on the cell array area. A plurality of first metal contacts may extend through the first gate structure layer in the first direction between the substate and the contact separation layer in the extension area. A plurality of second metal contacts may extend through the second gate structure layer in the first direction in the extension area. The contact separation layer may be between the first plurality of metal contacts and the second plurality of metal contacts, and each of the second metal contacts may be aligned with a respective one of the first metal contacts in the first direction. The device may also include a plurality of first electrode pads and a plurality of second electrode pads. Each of the first electrode pads may extend from a sidewall of a respective one of the first metal contacts to provide electrical coupling with a respective one of the first gate layers. Each of the second electrode pads may extend from a sidewall of a respective one of the second metal contacts to provide electrical coupling with a respective one of the second gate layers.

公开(公告)号：US20240371730A1

公开(公告)日：2024-11-07

申请号：US18411171

申请日：2024-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahreum Lee ,  Woosung Yang ,  Jimo Gu ,  Sukkang Sung

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

Abstract: Disclosed are semiconductor devices and semiconductor packages including the same. The semiconductor package includes a package substrate, and a first chip stack and a second chip stack that are stacked on the package substrate. Each of the first and second chip stacks includes a plurality of vertically stacked semiconductor chips. Each of the semiconductor chips includes a plurality of first vertical connection structures and a plurality of second vertical connection structures. The first vertical connection structures of the semiconductor chips in the second chip stack overlap and are connected with the second vertical connection structures of the semiconductor chips in the first chip stack.