公开(公告)号：US20240371730A1

公开(公告)日：2024-11-07

申请号：US18411171

申请日：2024-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahreum Lee ,  Woosung Yang ,  Jimo Gu ,  Sukkang Sung

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

Abstract: Disclosed are semiconductor devices and semiconductor packages including the same. The semiconductor package includes a package substrate, and a first chip stack and a second chip stack that are stacked on the package substrate. Each of the first and second chip stacks includes a plurality of vertically stacked semiconductor chips. Each of the semiconductor chips includes a plurality of first vertical connection structures and a plurality of second vertical connection structures. The first vertical connection structures of the semiconductor chips in the second chip stack overlap and are connected with the second vertical connection structures of the semiconductor chips in the first chip stack.

公开(公告)号：US11164887B2

公开(公告)日：2021-11-02

申请号：US16749110

申请日：2020-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yujin Seo ,  Byoungil Lee ,  Subin Kang ,  Jimo Gu

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

Abstract: A vertical memory device includes channels on a substrate, a channel connecting pattern, gate electrodes, and an etch stop pattern and a blocking pattern sequentially stacked. The channels extend in a first direction perpendicular to an upper surface of the substrate. The channel connecting pattern extends in a second direction parallel to the upper surface of the substrate to cover outer sidewalls of the channels. The gate electrodes are spaced apart from each other in the first direction on the channel connecting pattern, and extend in the second direction to surround the channels. The etch stop pattern and the blocking pattern are sequentially stacked in a third direction parallel to the upper surface of the substrate and crossing the second direction on an end portion of the channel connecting pattern in the third direction, and include different materials from each other.

公开(公告)号：US20240074173A1

公开(公告)日：2024-02-29

申请号：US18300022

申请日：2023-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahreum Lee ,  Woosung Yang ,  Jimo Gu ,  Jaeho Kim ,  Sukkang Sung

IPC: H10B41/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B41/27 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: According to some embodiments of inventive concepts, vertical nonvolatile memory devices and related methods may reduce chip size. The nonvolatile memory device may include a substrate wherein a first direction is orthogonal with respect to a surface of the substrate and wherein the substrate includes a cell array area and an extension area. A first gate structure layer on the substrate may include a plurality of first gate layers. A contact separation layer may be on the first gate structure layer on the extension area. A second gate structure layer on the first gate structure layer and on the contact separation layer may include a plurality of second gate layers. A plurality of channel structures may extend in the first direction through the first and second gate structure layers on the cell array area. A plurality of first metal contacts may extend through the first gate structure layer in the first direction between the substate and the contact separation layer in the extension area. A plurality of second metal contacts may extend through the second gate structure layer in the first direction in the extension area. The contact separation layer may be between the first plurality of metal contacts and the second plurality of metal contacts, and each of the second metal contacts may be aligned with a respective one of the first metal contacts in the first direction. The device may also include a plurality of first electrode pads and a plurality of second electrode pads. Each of the first electrode pads may extend from a sidewall of a respective one of the first metal contacts to provide electrical coupling with a respective one of the first gate layers. Each of the second electrode pads may extend from a sidewall of a respective one of the second metal contacts to provide electrical coupling with a respective one of the second gate layers.

公开(公告)号：US12082415B2

公开(公告)日：2024-09-03

申请号：US17375273

申请日：2021-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jimo Gu ,  Bumkyu Kang ,  Sungmin Hwang

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A semiconductor device includes a substrate, a lower stack structure on the substrate and including lower gate electrodes stacked apart from each other, an upper stack structure on the lower stack structure and including upper gate electrodes stacked apart from each other, a lower channel structure penetrating through the lower stack structure and including a lower channel layer, and a lower channel insulating layer on the lower channel layer the lower channel insulating layer surrounding a lower slit, and an upper channel structure penetrating through the upper stack structure and including an upper channel layer and an upper channel insulating layer on the upper channel layer, the upper channel insulating layer surrounding an upper slit. A width of the lower slit is greater than a width of the upper slit, and a thickness of the lower channel insulating layer is greater than a thickness of the upper channel insulating layer.

公开(公告)号：US11792990B2

公开(公告)日：2023-10-17

申请号：US17514331

申请日：2021-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yujin Seo ,  Byoungil Lee ,  Subin Kang ,  Jimo Gu

IPC: H01L27/11582 ,  H10B43/27 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/10 ,  H10B43/35

Abstract: A vertical memory device includes channels on a substrate, a channel connecting pattern, gate electrodes, and an etch stop pattern and a blocking pattern sequentially stacked. The channels extend in a first direction perpendicular to an upper surface of the substrate. The channel connecting pattern extends in a second direction parallel to the upper surface of the substrate to cover outer sidewalls of the channels. The gate electrodes are spaced apart from each other in the first direction on the channel connecting pattern, and extend in the second direction to surround the channels. The etch stop pattern and the blocking pattern are sequentially stacked in a third direction parallel to the upper surface of the substrate and crossing the second direction on an end portion of the channel connecting pattern in the third direction, and include different materials from each other.

公开(公告)号：US20230170302A1

公开(公告)日：2023-06-01

申请号：US17934743

申请日：2022-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jimo Gu ,  Jiyoung Kim ,  Woosung Yang ,  Sukkang Sung ,  Chang-Sup Lee

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: Disclosed are semiconductor devices and electronic systems including the same. A semiconductor device includes a substrate including a cell array region and a connection region, an electrode structure including electrodes and dielectric layers that are stacked in alternating fashion, each of the plurality of electrodes including an electrode part on the cell array region and a pad part on the connection region, dummy vertical structures on the connection region and penetrating the pad parts of each of the electrodes, and a cell contact plug on the connection region and coupled to the pad part of each of the electrodes. A thickness of the pad part is greater than that of the electrode part. The pad part has a lower portion connected to the electrode part and an upper portion on the lower portion. Between adjacent ones of the dummy vertical structures, a width of the upper portion is not less than that of the lower portion.