公开(公告)号：US20170117252A1

公开(公告)日：2017-04-27

申请号：US15221164

申请日：2016-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-hyun BAIK ,  Cheol-woo LEE ,  Wan-ho PARK

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L24/06 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A printed circuit board (PCB) for reducing a size of a semiconductor package and a semiconductor package including the same are provided. The PCB includes a substrate base including a chip attach area disposed on a top thereof, a top pad and a bottom pad respectively disposed on the top and a bottom of the substrate base, a first top solder resist layer formed on the top of the substrate base and including a first pad opening corresponding to the top pad and covering the chip attach area, a second top solder resist layer formed on the first top solder resist layer and including a second pad opening corresponding to the top pad and a chip attach opening corresponding to the chip attach area, and a bottom solder resist layer formed on the bottom of the substrate base and including a third pad opening corresponding to the bottom pad.

公开(公告)号：US20200013757A1

公开(公告)日：2020-01-09

申请号：US16572866

申请日：2019-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-sung KIM ,  Cheol-woo LEE

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/367 ,  H01L23/552

Abstract: A semiconductor package including a package base substrate; at least one semiconductor chip on the package base substrate; a heat sink attached on the at least one semiconductor chip, the heat sink including a base and a plurality of protrusion patterns on a top of the base; and a molding covering a top of the package base substrate, a side surface of the at least one semiconductor chip, and a side surface of the heat sink without covering a top of the heat sink.

公开(公告)号：US20190172816A1

公开(公告)日：2019-06-06

申请号：US16005749

申请日：2018-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-sung KIM ,  Cheol-woo LEE

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/367 ,  H01L23/552

CPC classification number: H01L25/0657 ,  H01L21/4882 ,  H01L21/56 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/552 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor package including a package base substrate; at least one semiconductor chip on the package base substrate; a heat sink attached on the at least one semiconductor chip, the heat sink including a base and a plurality of protrusion patterns on a top of the base; and a molding covering a top of the package base substrate, a side surface of the at least one semiconductor chip, and a side surface of the heat sink without covering a top of the heat sink.

公开(公告)号：US20160093545A1

公开(公告)日：2016-03-31

申请号：US14723976

申请日：2015-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheol-woo LEE ,  Kang Soo LEE ,  Hyeon HWANG

IPC: H01L23/06 ,  H01L21/56 ,  H01L21/52 ,  H01L23/482

CPC classification number: H01L23/4827 ,  H01L23/295 ,  H01L23/3135 ,  H01L23/562 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes: a package substrate; a semiconductor chip mounted on the package substrate and electrically connected to the package substrate; a first protective layer covering the semiconductor chip and having flexibility controlled by at least one of a material type, a thickness, a material composition ratio and viscosity of the first protective layer; and a second protective layer arranged on the first protective layer and having flexibility controlled by at least one of a material type and a thickness of the second protective layer, wherein the first protective layer comprises a first binder resin, a first hardener, and a first hardening catalyst. According to the semiconductor package of the inventive concept, protective layers protecting the semiconductor chip have flexibility, and thus, the semiconductor package may be bent.

Abstract translation: 提供半导体封装及其制造方法。 半导体封装包括：封装衬底; 半导体芯片，其安装在所述封装基板上并电连接到所述封装基板; 覆盖半导体芯片的第一保护层，并且具有由第一保护层的材料类型，厚度，材料组成比和粘度中的至少一种控制的柔性; 以及布置在所述第一保护层上并具有由所述第二保护层的材料类型和厚度中的至少一种控制的柔性的第二保护层，其中所述第一保护层包括第一粘合剂树脂，第一固化剂和第一保护层 硬化催化剂。 根据本发明构思的半导体封装，保护半导体芯片的保护层具有柔性，从而可以使半导体封装弯曲。

公开(公告)号：US20150102507A1

公开(公告)日：2015-04-16

申请号：US14511158

申请日：2014-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheol-woo LEE ,  Ji-han KO

IPC: H01L23/00

CPC classification number: H01L24/32 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49575 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/27 ,  H01L24/29 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/06135 ,  H01L2224/27003 ,  H01L2224/27436 ,  H01L2224/29082 ,  H01L2224/29084 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/3201 ,  H01L2224/32013 ,  H01L2224/32014 ,  H01L2224/32053 ,  H01L2224/32056 ,  H01L2224/32058 ,  H01L2224/32059 ,  H01L2224/32105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45169 ,  H01L2224/45184 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/4886 ,  H01L2224/48866 ,  H01L2224/48881 ,  H01L2224/48884 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/83856 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/8546 ,  H01L2224/92147 ,  H01L2224/92165 ,  H01L2224/92242 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/06 ,  H01L2924/10161 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/13091 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/14511 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/35 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/066 ,  H01L2924/05442 ,  H01L2224/83

Abstract: Provided is a semiconductor package that may prevent deformation of stacked semiconductor chips and minimize a semiconductor package size. The semiconductor package includes a package base substrate, a lower chip stacked on the package base substrate, an upper chip stacked on the lower chip, and a first die attach film (DAF) attached to a bottom surface of the upper chip to cover at least a portion of the lower chip. The first DAF may be a multi-layer film including a first attaching layer contacting the bottom surface of the upper chip and a second attaching layer attached to a bottom of the first attaching layer to cover at least a portion of a side surface of the lower chip.

Abstract translation: 提供了可以防止堆叠的半导体芯片的变形并使半导体封装尺寸最小化的半导体封装。 半导体封装包括封装基底基板，堆叠在封装基底基板上的下部芯片，堆叠在下部芯片上的上部芯片，以及附接到上部芯片的底表面上的至少覆盖的第一芯片附着膜（DAF） 下部芯片的一部分。 第一DAF可以是多层膜，其包括接触上芯片的底表面的第一附着层和附接到第一附着层的底部的第二附着层，以覆盖下层的侧表面的至少一部分 芯片。