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    Semiconductor devices having composite spacers containing different dielectric materials
    1.
    发明授权
    Semiconductor devices having composite spacers containing different dielectric materials 有权
    具有包含不同介电材料的复合间隔物的半导体器件

    公开(公告)号：US09275995B2

    公开(公告)日：2016-03-01

    申请号：US14543140

    申请日：2014-11-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jin-Bum Kim ,  Bon-Young Koo ,  Seok-Hoon Kim ,  Chul Kim ,  Kwan-Heum Lee ,  Byeong-Chan Lee ,  Su-Jin Jung

    IPC: H01L27/088 ,  H01L29/161 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L27/0886 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/785

    Abstract: An integrated circuit device includes an electrically conductive pattern on a substrate. This electrically conductive pattern may be a gate pattern of a field effect transistor. A first electrically insulating spacer is provided on a sidewall of the electrically conductive pattern. The first electrically insulating spacer includes a first lower spacer and a first upper spacer, which extends on the first lower spacer and has a side surface vertically aligned with a corresponding side surface of the first lower spacer. The first upper spacer has a greater dielectric constant relative to a dielectric constant of the first lower spacer. A pair of parallel channel regions may also be provided, which protrude from a surface of the substrate. The electrically conductive pattern may surround top and side surfaces of the pair of parallel channel regions.

    Abstract translation: 集成电路器件包括在衬底上的导电图案。 该导电图案可以是场效应晶体管的栅极图案。 第一电绝缘垫片设置在导电图案的侧壁上。 第一电绝缘间隔件包括第一下间隔件和第一上间隔件，其在第一下间隔件上延伸并且具有与第一下间隔件的对应侧表面垂直对准的侧表面。 第一上间隔物相对于第一下间隔物的介电常数具有更大的介电常数。 还可以设置一对平行的通道区域，其从衬底的表面突出。 导电图案可以围绕该对平行通道区域的顶表面和侧表面。

    Semiconductor devices
    2.
    发明授权
    Semiconductor devices 有权
    半导体器件

    公开(公告)号：US09112015B2

    公开(公告)日：2015-08-18

    申请号：US13921616

    申请日：2013-06-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Keum-Seok Park ,  Jung-Ho Yoo ,  Woo-Bin Song ,  Byeong-Chan Lee

    IPC: H01L29/76 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/165 ,  H01L21/8238

    CPC classification number: H01L29/78 ,  H01L21/823814 ,  H01L29/0684 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    Abstract: In a semiconductor device and a method of manufacturing the same, the semiconductor device includes a gate structure crossing an active region of a silicon substrate. Spacers are provided on both sides of the gate structure, respectively. Silicon patterns fill up recessed portions of the silicon substrate and on both sides of the spacers and has a shape protruding higher than a bottom surface of the gate structure, a lower edge of the protruded portion partially makes contact with a top surface of the isolation region, a first side and a second side of each of the silicon patterns, which are opposite to each other in a channel width direction in the gate structure, are inclined toward an inside of the active region. A highly doped impurity region is provided in the silicon patterns and doped with an N type impurity. The semiconductor device represents superior threshold voltage characteristics.

    Abstract translation: 在半导体器件及其制造方法中，半导体器件包括与硅衬底的有源区交叉的栅极结构。 分别设置在门结构的两侧。 硅图案填充硅衬底的凹陷部分并且在间隔物的两侧上并且具有高于栅极结构的底表面突出的形状，突出部分的下边缘部分地与隔离区域的顶表面接触 ，在栅极结构中的沟道宽度方向上彼此相对的每个硅图案的第一侧和第二侧朝向有源区域的内部倾斜。 在硅图案中提供高掺杂杂质区，并掺杂有N型杂质。 半导体器件表现出优异的阈值电压特性。

    Method for Fabricating Semiconductor Device
    3.
    发明申请
    Method for Fabricating Semiconductor Device 有权
    半导体器件制造方法

    公开(公告)号：US20140024192A1

    公开(公告)日：2014-01-23

    申请号：US13932047

    申请日：2013-07-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seok-Hoon Kim ,  Dong-Chan Suh ,  Byeong-Chan Lee

    IPC: H01L29/66

    CPC classification number: H01L29/6656 ,  H01L21/764 ,  H01L21/7682 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

    Abstract: A method for fabricating a semiconductor device comprises forming a dummy gate pattern and a spacer that is arranged on a sidewall of the dummy gate pattern on a substrate, forming an air gap on both sides of the dummy gate pattern by removing the spacer, exposing the substrate by removing the dummy gate pattern, and sequentially forming a gate insulating film including a high-k insulating film and a metal gate electrode on the exposed substrate.

    Abstract translation: 一种半导体器件的制造方法，其特征在于，在基板上形成伪栅极图案和间隔物，该间隔物配置在伪栅极图案的侧壁上，通过去除间隔物，在伪栅极图案的两面形成气隙， 通过去除伪栅极图案，并且在暴露的基板上顺序地形成包括高k绝缘膜和金属栅电极的栅极绝缘膜。

    Semiconductor Devices Having Shallow Junctions
    6.
    发明申请
    Semiconductor Devices Having Shallow Junctions 审中-公开
    具有浅接头的半导体器件

    公开(公告)号：US20140287564A1

    公开(公告)日：2014-09-25

    申请号：US14287546

    申请日：2014-05-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Keum-Seok Park ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sang-Bom Kang ,  Hong-Bum Park

    IPC: H01L29/66 ,  H01L29/08

    CPC classification number: H01L29/66621 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    Abstract: Semiconductor devices are provided including a substrate having a first surface and a second surface recessed from opposite sides of the first surface, a gate pattern formed on the first surface and having a gate insulating layer and a gate electrode, a carbon-doped silicon buffer layer formed on the second surface, and source and drain regions doped with an n-type dopant or p-type dopant, epitaxially grown on the silicon buffer layer to be elevated from a top surface of the gate insulating layer.

    Abstract translation: 提供了半导体器件，其包括具有从第一表面的相对侧凹入的第一表面和第二表面的衬底，形成在第一表面上并具有栅极绝缘层和栅电极的栅极图案，碳掺杂硅缓冲层 形成在第二表面上，以及掺杂有n型掺杂剂或p型掺杂剂的源极和漏极区，其外延生长在硅缓冲层上以从栅极绝缘层的顶表面升高。

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