公开(公告)号：US20180238824A1

公开(公告)日：2018-08-23

申请号：US15438734

申请日：2017-02-21

Applicant: QUALCOMM Incorporated

Inventor： Yong Ju LEE ,  Joung Won PARK

IPC: G01N27/327 ,  G01N27/414 ,  C12Q1/68 ,  G01N27/407 ,  C12Q1/00 ,  G01N33/487

CPC classification number: C12Q1/002 ,  C12Q1/6869 ,  C12Q1/6874 ,  C12Q2565/607 ,  G01N27/4145 ,  G01N33/48721 ,  C12Q2563/116 ,  C12Q2565/631

Abstract: The disclosure generally relates to a deoxyribonucleic acid (DNA) sequencing circuit having a controllable pore size and a lower membrane capacitance and noise floor relative to biological nanopore devices. For example, design principles used to fabricate a fin-shaped field effect transistor (FinFET) may be applied to form, on a first wafer, a nanopore that has a desired pore size in a silicon-based membrane. Electrodes and an interconnect embedded with an amplifier and analog-to-digital converter (ADC) may be formed on a separate second wafer, wherein the first wafer and the second wafer may then be bonded and further processed to form a sensing device that includes appropriate wells and pores to be used in a DNA sequencing circuit.

公开(公告)号：US20190024254A1

公开(公告)日：2019-01-24

申请号：US16141927

申请日：2018-09-25

Applicant: QUALCOMM Incorporated

Inventor： Yong Ju LEE ,  Vladimir APARIN

IPC: C25D7/12 ,  G01N33/487 ,  G01N27/30 ,  H01L21/285 ,  G01N27/447 ,  C25D3/46 ,  G01N27/414 ,  C25D5/48

Abstract: Techniques for increasing the lifespan of a nanopore DNA sensing device are disclosed. A related DNA sensing device may be formed by a process comprising forming a first electrode, forming a second electrode, disposing the first electrode and second electrode within an insulator, and disposing a lipid bilayer having a nanopore between the first electrode and second electrode. The forming of the second electrode may comprise forming a silver (Ag) layer, pressing a mold into the Ag layer to form a pattern in the Ag layer, removing the mold from the Ag layer, and exposing the Ag layer to an electrolyte.

公开(公告)号：US20180163266A1

公开(公告)日：2018-06-14

申请号：US15373007

申请日：2016-12-08

Applicant: QUALCOMM Incorporated

Inventor： Tallis Young CHANG ,  Yaoling PAN ,  Yong Ju LEE

IPC: C12Q1/68 ,  G01N27/447 ,  G01N33/487 ,  G03F7/20 ,  H01L27/092

CPC classification number: C12Q1/6869 ,  G01N33/48721 ,  H01L27/092 ,  C12Q2565/629

Abstract: Methods and apparatuses for sensing nucleotides are disclosed. A related nucleotide sensing device may include an insulator having an electrode well and a separation layer attached to the insulator, the separation layer including a film and a shell layer. The film may have a hole, the hole having a first diameter. The shell layer may be disposed on a surface of the film, and at least a portion of the shell layer may be disposed within the hole. The separation layer may be formed of inorganic material and may comprise a nanopore. The nanopore may permit fluid communication with the electrode well across the separation layer. The nanopore may be disposed within the hole and may have a second diameter smaller than the first diameter.

公开(公告)号：US20170271499A1

公开(公告)日：2017-09-21

申请号：US15073560

申请日：2016-03-17

Applicant: QUALCOMM Incorporated

Inventor： Yong Ju LEE

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/06 ,  H01L23/367 ,  H01L23/373 ,  H01L29/16

CPC classification number: H01L29/785 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02488 ,  H01L21/02527 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02546 ,  H01L23/367 ,  H01L23/3731 ,  H01L27/0211 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/1606 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/66795 ,  H01L29/6681

Abstract: According to various aspects, a thermal-aware finned field-effect transistor (FinFET) may have a design that can substantially reduce hot spot temperatures and resolve other self-heating problems. More particularly, the FinFET design may use aluminum nitride (AlN) fins that can provide a main thermal exit and a source, drain, and channel formed from materials that can spread or dissipate heat, wherein AlN has a high thermal conductivity compared to silicon such that using AlN to form the fins may substantially increase heat flux to a silicon substrate relative to silicon fins. Furthermore, thermal-efficient materials may be used to form the source, drain, and channel structures to further spread heat and decrease hot spot temperatures.

公开(公告)号：US20170338311A1

公开(公告)日：2017-11-23

申请号：US15158653

申请日：2016-05-19

Applicant: QUALCOMM Incorporated

Inventor： Yong Ju LEE ,  Yang DU

IPC: H01L29/16 ,  H01L21/02 ,  H01L29/66 ,  H01L21/027 ,  H01L29/10 ,  H01L29/08 ,  H01L23/535 ,  H01L21/04 ,  H01L29/786 ,  H01L29/51

CPC classification number: H01L29/1606 ,  H01L21/02112 ,  H01L21/02378 ,  H01L21/02527 ,  H01L21/0272 ,  H01L21/0273 ,  H01L21/044 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66045 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/78684

Abstract: An n-type metal-oxide-semiconductor (NMOS) transistor comprises a graphene channel with a chemically adsorbed nitrogen dioxide (NO2) layer formed thereon. The NMOS transistor may comprise a substrate having a graphene layer formed thereon and a gate stack formed on a portion of the graphene layer disposed in a channel region that further includes a spacer region. The gate stack may comprise the chemically adsorbed NO2 layer formed on the graphene channel, a high-k dielectric formed over the adsorbed NO2 layer, a gate metal formed over the high-k dielectric, and spacer structures formed in the spacer region. The adsorbed NO2 layer formed under the gate and the spacer structures may therefore attract electrons from the graphene channel to turn the graphene-based NMOS transistor off at a gate voltage (Vg) equal to zero, making the graphene-based NMOS transistor suitable for digital logic applications.

公开(公告)号：US20170321342A1

公开(公告)日：2017-11-09

申请号：US15587373

申请日：2017-05-04

Applicant: QUALCOMM Incorporated

Inventor： Yong Ju LEE ,  Vladimir APARIN

IPC: C25D7/12 ,  G01N27/447 ,  G01N27/414 ,  C25D5/48 ,  H01L21/285 ,  C25D3/46

CPC classification number: C25D7/123 ,  C25D3/46 ,  C25D5/48 ,  G01N27/301 ,  G01N27/4145 ,  G01N27/4146 ,  G01N27/44791 ,  G01N33/48721 ,  H01L21/2855

Abstract: Techniques for increasing the lifespan of a nanopore DNA sensing device are disclosed. A related method may include forming a first electrode, forming a second electrode, disposing the first electrode and second electrode within an insulator, and disposing a lipid bilayer having a nanopore between the first electrode and second electrode. The forming of the second electrode may comprise forming a silver (Ag) layer, pressing a mold into the Ag layer to form a pattern in the Ag layer, removing the mold from the Ag layer, and exposing the Ag layer to an electrolyte.

公开(公告)号：US20180038830A1

公开(公告)日：2018-02-08

申请号：US15226859

申请日：2016-08-02

Applicant: QUALCOMM Incorporated

Inventor： Yong Ju LEE ,  Joung Won PARK ,  Vladimir APARIN

IPC: G01N27/447 ,  C12Q1/68

Abstract: Techniques for improving the DNA sensing signal of nanopore-based DNA sensing devices are disclosed. A related DNA sensing device may include a first electrode, a second electrode, a hydrophobic layer having a nanopore disposed therein, and a negative capacitance layer.

公开(公告)号：US20160093591A1

公开(公告)日：2016-03-31

申请号：US14498965

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Jeffrey LAN ,  Wenyue ZHANG ,  Yang DU ,  Yong Ju LEE ,  Shiqun GU ,  Jing XIE

IPC: H01L25/065 ,  H01L27/06 ,  H01L21/762 ,  H01L21/768 ,  H01L21/683 ,  H01L21/265 ,  H01L23/528 ,  H01L23/522 ,  H01L25/00 ,  H01L21/02

CPC classification number: H01L25/0657 ,  H01L21/02164 ,  H01L21/265 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/8221 ,  H01L23/5226 ,  H01L23/528 ,  H01L25/50 ,  H01L27/0688 ,  H01L2221/68318 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A microelectromechanical system (MEMS) bond release structure is provided for manufacturing of three-dimensional integrated circuit (3D IC) devices with two or more tiers. The MEMS bond release structure includes a MEMS sacrificial release layer which may have a pillar or post structure, or alternatively, a continuous sacrificial layer for bonding and release.

Abstract translation: 提供了用于制造具有两层或多层的三维集成电路（3D IC）装置的微机电系统（MEMS）键释放结构。 MEMS键释放结构包括可以具有柱或柱结构的MEMS牺牲脱离层，或者替代地，用于粘合和释放的连续牺牲层。