知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

10 records (took 0.012 seconds)

    DIODE-BASED TEMPERATURE SENSOR
    3.
    发明申请
    DIODE-BASED TEMPERATURE SENSOR 审中-公开

    公开(公告)号：US20190086272A1

    公开(公告)日：2019-03-21

    申请号：US15706734

    申请日：2017-09-17

    Applicant: QUALCOMM Incorporated

    Inventor： William XIA ,  Yang DU

    IPC: G01K7/01 ,  G01K3/00 ,  G01K7/02

    CPC classification number: G01K7/01 ,  G01K3/005 ,  G01K7/02

    Abstract: Disclosed is a system for measuring temperature in an integrated circuit (IC) device. The system includes a diode-based temperature sensor comprising a first plurality of diodes coupled between a power supply pin of the IC device and a ground pin of the IC device and a second plurality of diodes coupled between the power supply pin and the ground pin, and a voltage sensing circuit configured to detect a voltage difference between the first plurality of diodes and the second plurality of diodes.

    DUAL POWER SWING PIPELINE DESIGN WITH SEPARATION OF COMBINATIONAL AND SEQUENTIAL LOGICS
    5.
    发明申请
    DUAL POWER SWING PIPELINE DESIGN WITH SEPARATION OF COMBINATIONAL AND SEQUENTIAL LOGICS 有权
    具有分离组合和顺序逻辑的双功率振荡管道设计

    公开(公告)号：US20160261269A1

    公开(公告)日：2016-09-08

    申请号：US14638270

    申请日：2015-03-04

    Applicant: QUALCOMM Incorporated

    Inventor： Jing XIE ,  Yang DU

    IPC: H03K19/00 ,  H03K19/0175 ,  H03K3/037

    CPC classification number: H03K19/0021 ,  G06F1/3296 ,  H01L25/0657 ,  H03K3/037 ,  H03K19/017509 ,  Y02D10/172

    Abstract: A three-dimensional integrated circuit having a dual or multiple power domain is capable of less energy consumption operation under a given clock rate, which results in an enhanced power-performance-area (PPA) envelope. Sequential logic operates under a system clock that determines the system throughput, whereas combinational logic operates in a different power domain to control overall system power including dynamic and static power. The sequential logic and clock network may be implemented in one tier of the three-dimensional integrated circuit supplied with a relatively high power supply voltage, whereas the combinational logic may be implemented in another tier of the three-dimensional integrated circuit supplied with a relatively low power supply voltage. Further pipeline reorganization may be implemented to leverage the system energy consumption and performance to an optimal point.

    Abstract translation: 具有双功率域或多个功率域的三维集成电路在给定的时钟速率下能够更少的能量消耗操作，这导致增强的功率性能面积（PPA）包络。 顺序逻辑在确定系统吞吐量的系统时钟下运行，而组合逻辑在不同的功率域中运行，以控制整个系统功率，包括动态和静态功率。 顺序逻辑和时钟网络可以在被提供有相对高的电源电压的三维集成电路的一个层中实现，而组合逻辑可以在提供有相对低的三维集成电路的另一层中实现 电源电压。 可以实施进一步的管道重组以将系统能量消耗和性能用于最佳点。

    INTELLECTUAL PROPERTY BLOCK DESIGN WITH FOLDED BLOCKS AND DUPLICATED PINS FOR 3D INTEGRATED CIRCUITS
    6.
    发明申请
    INTELLECTUAL PROPERTY BLOCK DESIGN WITH FOLDED BLOCKS AND DUPLICATED PINS FOR 3D INTEGRATED CIRCUITS 有权
    用于3D集成电路的具有折叠块和重复PINS的知识产权块设计

    公开(公告)号：US20160232271A1

    公开(公告)日：2016-08-11

    申请号：US14617896

    申请日：2015-02-09

    Applicant: QUALCOMM Incorporated

    Inventor： Sung Kyu LIM ,  Kambiz SAMADI ,  Yang DU

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  H01L27/0688

    Abstract: An intellectual property (IP) block design methodology for three-dimensional (3D) integrated circuits may comprise folding at least one two-dimensional (2D) block that has one or more circuit components into a 3D block that has multiple tiers, wherein the one or more circuit components in the folded 2D block may be distributed among the multiple tiers in the 3D block. Furthermore, one or more pins may be duplicated across the multiple tiers in the 3D block and the one or more duplicated pins may be connected to one another using one or more intra-block through-silicon-vias (TSVs) placed inside the 3D block.

    Abstract translation: 用于三维（3D）集成电路的知识产权（IP）块设计方法可以包括将具有一个或多个电路组件的至少一个二维（2D）块折叠到具有多个层的3D块中，其中， 折叠的2D块中的多个电路组件可以分布在3D块中的多个层中。 此外，一个或多个引脚可以跨越3D块中的多个层复制，并且一个或多个复制引脚可以使用放置在3D块内部的一个或多个块内穿通硅通孔（TSV）彼此连接 。

    HIGH QUALITY PHYSICAL DESIGN FOR MONOLITHIC THREE-DIMENSIONAL INTEGRATED CIRCUITS (3D IC) USING TWO-DIMENSIONAL INTEGRATED CIRCUIT (2D IC) DESIGN TOOLS
    8.
    发明申请
    HIGH QUALITY PHYSICAL DESIGN FOR MONOLITHIC THREE-DIMENSIONAL INTEGRATED CIRCUITS (3D IC) USING TWO-DIMENSIONAL INTEGRATED CIRCUIT (2D IC) DESIGN TOOLS 审中-公开
    使用二维集成电路（2D IC）设计工具的单片三维集成电路（3D IC）的高品质物理设计

    公开(公告)号：US20160042110A1

    公开(公告)日：2016-02-11

    申请号：US14638323

    申请日：2015-03-04

    Applicant: QUALCOMM Incorporated

    Inventor： Sung Kyu LIM ,  Kambiz SAMADI ,  Pratyush KAMAL ,  Yang DU

    IPC: G06F17/50

    CPC classification number: G06F17/5072

    Abstract: A method of designing a multi-tier three-dimensional integrated circuit (3D IC) is provided that allows the use of two-dimensional integrated circuit (2D IC) design tools. When a 2D IC design tool is used, a macro for each of the tiers indicating areas available and unavailable for placement of circuit elements in each tier is created, and the macros are superimposed on one another. Circuit elements to be implemented in the 3D IC, such as logic cells and interconnects, are shrunk and then placed and repopulated on the superimposed macro. The repopulated circuit elements on the superimposed macro are then partitioned into tiers. Monolithic inter-tier via (MIV) placement and tier-to-tier routing are designed to provide electrical connections between circuit elements in different tiers. Power, performance and area (PPA) optimization may also be performed to optimize the 3D IC layout.

    Abstract translation: 提供了一种设计多层三维集成电路（3D IC）的方法，其允许使用二维集成电路（2D IC）设计工具。 当使用2D IC设计工具时，会创建每个层级的宏，指示可用和不可用于在每个层中放置电路元件的区域，并且宏彼此叠加。 要在3D IC中实现的电路元件（例如逻辑单元和互连）被收缩，然后放置并重新填充在叠加的宏上。 然后将重叠的宏上的重新填充的电路元素分成几层。 单层跨层通过（MIV）放置和层到层布线被设计为在不同层级的电路元件之间提供电连接。 也可以执行功率，性能和面积（PPA）优化来优化3D IC布局。

    ULTRA-LOW POWER NEUROMORPHIC ARTIFICIAL INTELLIGENCE COMPUTING ACCELERATOR
    9.
    发明申请
    ULTRA-LOW POWER NEUROMORPHIC ARTIFICIAL INTELLIGENCE COMPUTING ACCELERATOR 审中-公开

    公开(公告)号：US20190073585A1

    公开(公告)日：2019-03-07

    申请号：US16119929

    申请日：2018-08-31

    Applicant: QUALCOMM Incorporated

    Inventor： Yu PU ,  Yang DU

    IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

    Abstract: A three-dimensional (3D) ultra-low power neuromorphic accelerator is described. The 3D ultra-low power neuromorphic accelerator includes a power manager as well as multiple tiers. The 3D ultra-low power neuromorphic accelerator also includes multiple cores defined on each tier and coupled to the power manager. Each core includes at least a processing element, a non-volatile memory, and a communications module.

    CLOCK TREE SYNTHESIS FOR LOW COST PRE-BOND TESTING OF 3D INTEGRATED CIRCUITS
    10.
    发明申请
    CLOCK TREE SYNTHESIS FOR LOW COST PRE-BOND TESTING OF 3D INTEGRATED CIRCUITS 有权
    用于3D集成电路低成本预结晶测试的时钟合成

    公开(公告)号：US20160233134A1

    公开(公告)日：2016-08-11

    申请号：US14617901

    申请日：2015-02-09

    Applicant: QUALCOMM Incorporated

    Inventor： Sung Kyu LIM ,  Kambiz SAMADI ,  Pratyush KAMAL ,  Yang DU

    IPC: H01L21/66 ,  H01L25/00 ,  H01L23/538 ,  H01L25/065

    CPC classification number: H01L22/20 ,  H01L22/32 ,  H01L23/5256 ,  H01L23/5382 ,  H01L23/5384 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06596

    Abstract: To enable low cost pre-bond testing for a three-dimensional (3D) integrated circuit, a backbone die may have a fully connected two-dimensional (2D) clock tree and one or more non-backbone die may have multiple isolated 2D clock trees. In various embodiments, clock sinks on the backbone die and the non-backbone die can be connected using multiple through-silicon-vias and the isolated 2D clock trees in the non-backbone die can be further connected via a Detachable tree (D-tree), which may comprise a rectilinear minimum spanning tree representing a shortest interconnect among the sinks associated with the 2D clock trees in the non-backbone die. Accordingly, the backbone die and the non-backbone die can be separated and individually tested prior to bonding using one clock probe pad, and the D-tree may be easily removed from the non-backbone die subsequent to the pre-bond testing by burning fuses at the sinks associated with the 2D clock trees.

    Abstract translation: 为了实现三维（3D）集成电路的低成本预键测试，主干管芯可以具有完全连接的二维（2D）时钟树，并且一个或多个非主干管芯可以具有多个隔离的2D时钟树 。 在各种实施例中，可以使用多个通硅通孔来连接骨干管芯和非骨干管芯上的时钟汇聚点，并且非骨干管芯中的隔离的2D时钟树可以通过可分离树（D-tree）进一步连接 ），其可以包括表示与非主干管芯中的2D时钟树相关联的汇之间的最短互连的直线最小生成树。 因此，在使用一个时钟探针焊盘进行粘合之前，主骨架和非主干裸片可以被分离和单独测试，并且在通过燃烧进行预键合测试之前，D树可以容易地从非主干模具移除 在与2D时钟树相关联的接收器处保险丝。

Patent Agency Ranking