公开(公告)号：US20160233853A1

公开(公告)日：2016-08-11

申请号：US14617885

申请日：2015-02-09

Applicant: QUALCOMM Incorporated

Inventor： Pratyush KAMAL

IPC: H03K3/356 ,  H03K3/3562 ,  H03K3/012

CPC classification number: H03K3/356182 ,  G11C19/28 ,  G11C19/34 ,  H01L27/0688 ,  H03K3/012 ,  H03K3/35606 ,  H03K3/35625

Abstract: A 3D multi-bit flip-flop may include a two tier structure. The two tier structure may include a first tier containing a common clock circuit for the multi-bit flip-flop as well as the clock driven portions of the individual flip-flops and a second tier containing a common scan circuit for the multi-bit flip-flop as well as the non-clock driven portions of the individual flip-flops. Alternatively, the first tier may include the common clock circuit as well as a portion of the individual flip-flops and the second tier may include the common scan circuit as well as the other portion of the individual flip-flops.

Abstract translation: 3D多位触发器可以包括两层结构。 双层结构可以包括第一层，其包含用于多位触发器的公共时钟电路以及各个触发器的时钟驱动部分，以及包含用于多位触发器的公共扫描电路的第二层 -flop以及各个触发器的非时钟驱动部分。 或者，第一层可以包括公共时钟电路以及单个触发器的一部分，并且第二层可以包括公共扫描电路以及各个触发器的另一部分。

公开(公告)号：US20160042110A1

公开(公告)日：2016-02-11

申请号：US14638323

申请日：2015-03-04

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu LIM ,  Kambiz SAMADI ,  Pratyush KAMAL ,  Yang DU

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method of designing a multi-tier three-dimensional integrated circuit (3D IC) is provided that allows the use of two-dimensional integrated circuit (2D IC) design tools. When a 2D IC design tool is used, a macro for each of the tiers indicating areas available and unavailable for placement of circuit elements in each tier is created, and the macros are superimposed on one another. Circuit elements to be implemented in the 3D IC, such as logic cells and interconnects, are shrunk and then placed and repopulated on the superimposed macro. The repopulated circuit elements on the superimposed macro are then partitioned into tiers. Monolithic inter-tier via (MIV) placement and tier-to-tier routing are designed to provide electrical connections between circuit elements in different tiers. Power, performance and area (PPA) optimization may also be performed to optimize the 3D IC layout.

Abstract translation: 提供了一种设计多层三维集成电路（3D IC）的方法，其允许使用二维集成电路（2D IC）设计工具。 当使用2D IC设计工具时，会创建每个层级的宏，指示可用和不可用于在每个层中放置电路元件的区域，并且宏彼此叠加。 要在3D IC中实现的电路元件（例如逻辑单元和互连）被收缩，然后放置并重新填充在叠加的宏上。 然后将重叠的宏上的重新填充的电路元素分成几层。 单层跨层通过（MIV）放置和层到层布线被设计为在不同层级的电路元件之间提供电连接。 也可以执行功率，性能和面积（PPA）优化来优化3D IC布局。

公开(公告)号：US20220020735A1

公开(公告)日：2022-01-20

申请号：US16928939

申请日：2020-07-14

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Jonghae KIM ,  Periannan CHIDAMBARAM ,  Pratyush KAMAL

IPC: H01L25/18 ,  H01L21/762 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00

Abstract: An integrated circuit (IC) package is described. The IC package includes a power delivery network. The IC package also includes a first die having a first surface and a second surface, opposite the first surface. The second surface is on a first surface of the power delivery network. The IC package further includes a second die having a first surface on the first surface of the first die. The IC package also includes package bumps on a second surface of the power delivery network, opposite the first surface of the power delivery network. The package bumps are coupled to contact pads of the power delivery network.

公开(公告)号：US20160233134A1

公开(公告)日：2016-08-11

申请号：US14617901

申请日：2015-02-09

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu LIM ,  Kambiz SAMADI ,  Pratyush KAMAL ,  Yang DU

IPC: H01L21/66 ,  H01L25/00 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L22/20 ,  H01L22/32 ,  H01L23/5256 ,  H01L23/5382 ,  H01L23/5384 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06596

Abstract: To enable low cost pre-bond testing for a three-dimensional (3D) integrated circuit, a backbone die may have a fully connected two-dimensional (2D) clock tree and one or more non-backbone die may have multiple isolated 2D clock trees. In various embodiments, clock sinks on the backbone die and the non-backbone die can be connected using multiple through-silicon-vias and the isolated 2D clock trees in the non-backbone die can be further connected via a Detachable tree (D-tree), which may comprise a rectilinear minimum spanning tree representing a shortest interconnect among the sinks associated with the 2D clock trees in the non-backbone die. Accordingly, the backbone die and the non-backbone die can be separated and individually tested prior to bonding using one clock probe pad, and the D-tree may be easily removed from the non-backbone die subsequent to the pre-bond testing by burning fuses at the sinks associated with the 2D clock trees.

Abstract translation: 为了实现三维（3D）集成电路的低成本预键测试，主干管芯可以具有完全连接的二维（2D）时钟树，并且一个或多个非主干管芯可以具有多个隔离的2D时钟树 。 在各种实施例中，可以使用多个通硅通孔来连接骨干管芯和非骨干管芯上的时钟汇聚点，并且非骨干管芯中的隔离的2D时钟树可以通过可分离树（D-tree）进一步连接 ），其可以包括表示与非主干管芯中的2D时钟树相关联的汇之间的最短互连的直线最小生成树。 因此，在使用一个时钟探针焊盘进行粘合之前，主骨架和非主干裸片可以被分离和单独测试，并且在通过燃烧进行预键合测试之前，D树可以容易地从非主干模具移除 在与2D时钟树相关联的接收器处保险丝。