公开(公告)号：US20240421128A1

公开(公告)日：2024-12-19

申请号：US18335532

申请日：2023-06-15

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  Yi-Hang LIN ,  Dongming HE ,  Lily ZHAO ,  Ryan LANE

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L27/02

Abstract: Disclosed is a semiconductor device. In an aspect, a semiconductor device includes: a first-tier passive device including a substrate portion, a passive device portion, and a metallization portion disposed in a stacked configuration; and one or more second-tier passive devices disposed over the first-tier passive device. Each one of the one or more second-tier passive devices includes: a substrate portion, a passive device portion, and a metallization portion disposed in a stacked configuration; and a set of through substrate vias (TSVs) passing through a corresponding substrate portion and electrically coupled to a corresponding metallization portion. The semiconductor device comprises a passive component including the passive device portion of the first-tier passive device electrically coupled to one or more passive device portions of the one or more second-tier passive devices through the metallization portions of the first-tier passive device and the one or more second-tier passive devices.

公开(公告)号：US20220149005A1

公开(公告)日：2022-05-12

申请号：US17094303

申请日：2020-11-10

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  Li-Sheng WENG ,  Zhimin SONG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56 ,  H01L23/31

Abstract: A package comprising a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, an interconnect integrated device coupled to the first integrated device and the second integrated device, and an underfill. The substrate includes a cavity. The interconnect integrated device is located over the cavity of the substrate. The underfill is located (i) between the first integrated device and the substrate, (ii) between the second integrated device and the substrate, (iii) between the interconnect integrated device and the first integrated device, and (iv) between the interconnect integrated device and the second integrated device.

公开(公告)号：US20210375742A1

公开(公告)日：2021-12-02

申请号：US16888516

申请日：2020-05-29

Applicant: QUALCOMM Incorporated

Inventor： Yue LI ,  Li-Sheng WENG ,  Yangyang SUN

IPC: H01L23/50 ,  H01L23/00

Abstract: An integrated circuit (IC) package is described. The IC package includes a die, having a pad layer structure on back-end-of-line layers on a substrate. The die also includes a metallization routing layer on the pad layer structure, and a first under bump metallization layer on the metallization routing layer. The IC package also includes a patterned seed layer on a surface of the die to contact the first under bump metallization layer. The IC package further includes a first package bump on the first under bump metallization layer.

公开(公告)号：US20250087611A1

公开(公告)日：2025-03-13

申请号：US18465717

申请日：2023-09-12

Applicant: QUALCOMM Incorporated

Inventor： Yujen CHEN ,  Yangyang SUN ,  Wei WANG

IPC: H01L23/00

Abstract: An integrated device comprising a die substrate; a plurality of pads; a plurality of inner solder interconnects coupled to the plurality of pads; and a plurality of pillar shell interconnects coupled to the plurality of inner solder interconnects. The plurality of inner solder interconnects are located between the plurality of pillar shell interconnects and the plurality of pads.

公开(公告)号：US20220320026A1

公开(公告)日：2022-10-06

申请号：US17213875

申请日：2021-03-26

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  Rong ZHOU ,  Li-Sheng WENG ,  Lily ZHAO

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/538 ,  H01L25/065 ,  H01L23/31

Abstract: A package that includes a substrate comprising a cavity, a first integrated device coupled to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects, a second integrated device coupled to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects, and a plurality of wire bonds coupled to the first integrated device and the second integrated device, wherein the plurality of wire bonds is located over the cavity of the substrate.

公开(公告)号：US20210118834A1

公开(公告)日：2021-04-22

申请号：US17071432

申请日：2020-10-15

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  John HOLMES ,  Xuefeng ZHANG ,  Dongming HE

IPC: H01L23/00

Abstract: Disclosed are devices, fabrication methods and design rules for flip-chip devices. Aspects include an apparatus including a flip-chip device. The flip-chip device including a die having a plurality of under bump metallizations (UBMs). A package substrate having a plurality of bond pads is also included. A plurality of solder joints coupling the die to the package substrate. The plurality of solder joints are formed from a plurality of solder bumps plated on the plurality of UBMs, where the plurality of solder bumps are directly connected to the plurality of bond pads.

公开(公告)号：US20190206984A1

公开(公告)日：2019-07-04

申请号：US15860005

申请日：2018-01-02

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Jun CHEN ,  Yangyang SUN ,  Stanley Seungchul SONG ,  Giridhar NALLAPATI

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L28/91 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5283

Abstract: Aspects of the disclosure are directed to an integrated circuit. The integrated circuit may include a substrate, a first group of metal layers including a plurality of first fingers over the substrate, wherein the first fingers are formed without a via. The integrated circuit may further include a second group of metal layers including a plurality of second fingers over the first group of metal layers, wherein the second fingers are formed with vias, and wherein the first and the second group of metal layers are formed by a processing technology node of 7 nm or below.

公开(公告)号：US20240371806A1

公开(公告)日：2024-11-07

申请号：US18313020

申请日：2023-05-05

Applicant: QUALCOMM Incorporated

Inventor： Dongming HE ,  Jun CHEN ,  Yangyang SUN ,  Lily ZHAO ,  Ahmer SYED

IPC: H01L23/00 ,  H01L23/31

Abstract: Disclosed are techniques for integrated circuit device. In an aspect, an integrated circuit device includes a metallization structure that includes a top metal layer structure; a passivation layer on the metallization structure; a bump structure disposed on the first bump line structure; and a first polymer protection layer. The passivation layer may include one or more first openings. The first bump line structure may include one or more first extended portions respectively extending toward the top metal layer structure through the one or more first openings. The bump structure may be electrically coupled to the first bump line structure. The first polymer protection layer may be on the passivation layer, on a portion of the first bump line structure, and in contact with a side surface of the first bump line structure.

公开(公告)号：US20240055383A1

公开(公告)日：2024-02-15

申请号：US17819269

申请日：2022-08-11

Applicant: QUALCOMM Incorporated

Inventor： Dongming HE ,  Hung-Yuan HSU ,  Yangyang SUN ,  Lily ZHAO

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/13 ,  H01L24/04 ,  H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/03912 ,  H01L2224/0345 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05562 ,  H01L2224/05573 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/13016 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/11849 ,  H01L2224/11462 ,  H01L2224/11912

Abstract: Disclosed are techniques for selectively boosting conductive pillar bumps. In an aspect, an apparatus includes a plurality of metal pads, a first set of boosting pads attached to a first set of the plurality of metal pads, a first set of conductive pillar bumps attached to the first set of boosting pads, a second set of conductive pillar bumps attached to a second set of the plurality of metal pads, wherein heights of the first set of conductive pillar bumps are shorter than heights of the second set of conductive pillar bumps, and wherein heights of the first set of boosting pads plus the heights of the first set of conductive pillar bumps are within a tolerance threshold of the heights of the second set of conductive pillar bumps, and solder attached to the first set of conductive pillar bumps and the second set of conductive pillar bumps.

公开(公告)号：US20230369261A1

公开(公告)日：2023-11-16

申请号：US17741998

申请日：2022-05-11

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  Zhijie WANG ,  Wei WANG ,  Marcus HSU

IPC: H01L23/00 ,  H01L23/28 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L23/28 ,  H01L24/18 ,  H01L24/29 ,  H01L24/73 ,  H01L25/0657 ,  H01L24/03 ,  H01L2224/039 ,  H01L2224/0346 ,  H01L2224/05647 ,  H01L2224/18 ,  H01L2224/03436

Abstract: A package comprising a first substrate; a first integrated device coupled to the first substrate; an interconnection die coupled to the first substrate; a second substrate coupled to the first substrate through the interconnection die such that the first integrated device and the interconnection die are located between the first substrate and the second substrate; and an encapsulation layer coupled to the first substrate and the second substrate, wherein the encapsulation layer is located between the first substrate and the second substrate.