公开(公告)号：US20240355381A1

公开(公告)日：2024-10-24

申请号：US18306167

申请日：2023-04-24

Applicant: QUALCOMM Incorporated

Inventor： Seohee KIM ,  Chulmin JUNG ,  Xiao CHEN ,  Hanil LEE ,  Venugopal BOYNAPALLI ,  Jung Pill KIM

IPC: G11C11/413 ,  H03K5/24 ,  H10B10/00

CPC classification number: G11C11/413 ,  H03K5/24 ,  H10B10/18

Abstract: An integrated circuit is disclosed that includes a power supply multiplexer for selecting between a first power supply voltage and a second power supply voltage to provide a selected power supply voltage to a memory. A controller includes a comparator stage having a comparator with switchable inputs so that the comparator stage may control a binary state of a first output signal responsive to whether the first power supply voltage is greater than the second power supply voltage plus a voltage offset of the comparator. Similarly, the comparator stage may control a binary state of a second output signal responsive to whether the first power supply voltage is greater than the second power supply voltage minus the voltage offset. The controller controls the selection by the power supply multiplexer responsive to the binary states of the first and second output signals.

公开(公告)号：US20240266342A1

公开(公告)日：2024-08-08

申请号：US18165259

申请日：2023-02-06

Applicant: QUALCOMM Incorporated

Inventor： Renukprasad HIREMATH ,  Hyeokjin LIM ,  Foua VANG ,  Manjanaika CHANDRANAIKA ,  Seung Hyuk KANG ,  Venugopal BOYNAPALLI

IPC: H01L27/02 ,  G06F30/392

CPC classification number: H01L27/0207 ,  G06F30/392

Abstract: A chip includes a first column including first rails extending in a first direction, the first rails having a first pitch. The chip also includes a second column including second rails extending in the first direction, the second rails having a second pitch different from the first pitch. The chip also includes a transition region between the first column and the second column.

公开(公告)号：US20240250669A1

公开(公告)日：2024-07-25

申请号：US18156975

申请日：2023-01-19

Applicant: QUALCOMM Incorporated

Inventor： Ramaprasath VILANGUDIPITCHAI ,  Rui CHEN ,  Seung Hyuk KANG ,  Venugopal BOYNAPALLI

IPC: H03K3/037

CPC classification number: H03K3/0372 ,  H03K3/012

Abstract: A hybrid flop tray, including: a set of flip-flops cascaded along a scan path, wherein a first subset of one or more of the flip-flops of the set includes fin field effect transistors (FinFETs) each sized with a first number of fins, and a second subset of one or more of the flip-flops of the set includes FinFETs each sized with a second number of fins, wherein the first number of fins is different than the second number of fins; and a control circuit configured to provide control signals to the set of flip-flops.

公开(公告)号：US20220068360A1

公开(公告)日：2022-03-03

申请号：US17002082

申请日：2020-08-25

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu PALLERLA ,  Changho JUNG ,  Sung SON ,  Jason CHENG ,  Yandong GAO ,  Chulmin JUNG ,  Venugopal BOYNAPALLI

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4074 ,  G11C5/02

Abstract: A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.

公开(公告)号：US20240170488A1

公开(公告)日：2024-05-23

申请号：US17993594

申请日：2022-11-23

Applicant: QUALCOMM Incorporated

Inventor： Renukprasad HIREMATH ,  Keyurkumar Karsanbhai KANSAGRA ,  Shashikumar GANESH BHAT ,  Hyeokjin LIM ,  Seung Hyuk KANG ,  Venugopal BOYNAPALLI ,  Kamesh MEDISETTI

IPC: H01L27/118 ,  H03K19/094

CPC classification number: H01L27/11807 ,  H03K19/094 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11881 ,  H01L2027/11885

Abstract: An integrated circuit (IC) cell including: a first logic gate comprising a first polysilicon structure and a first pin; a second logic gate comprising a second polysilicon structure and a second pin, wherein the second polysilicon structure is spaced apart and adjacent to the first polysilicon structure in a cell row direction; and a source region, common to the first and second logic gates, situated between the first and second polysilicon structures, wherein the first and second pins are on a first metal track directly over the common source region.

公开(公告)号：US20220094363A1

公开(公告)日：2022-03-24

申请号：US17030087

申请日：2020-09-23

Applicant: QUALCOMM Incorporated

Inventor： Foua VANG ,  Hyeokjin LIM ,  Seung Hyuk KANG ,  Venugopal BOYNAPALLI ,  Shitiz ARORA

IPC: H03K19/094 ,  H01L23/528

Abstract: A MOS IC includes a MOS logic cell that includes first and second sets of transistor logic in first and second subcells, respectively. The first and second sets of transistor logic are functionally isolated from each other. The MOS logic cell includes a first set of Mx layer interconnects on an Mx layer extending in a first direction over the first and second subcells. A first subset of the first set of Mx layer interconnects is coupled to inputs/outputs of the first set of transistor logic in the first subcell and is unconnected to the second set of transistor logic. Each of the first subset of the first set of Mx layer interconnects extends from the corresponding input/output of the first set of transistor logic of the first subcell to the second subcell, and is the corresponding input/output of the first set of transistor logic.

公开(公告)号：US20200176562A1

公开(公告)日：2020-06-04

申请号：US16781820

申请日：2020-02-04

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong CHEN ,  Venugopal BOYNAPALLI ,  Hyeokjin LIM

IPC: H01L29/06 ,  H01L27/02 ,  H01L27/118 ,  H01L23/528 ,  H01L29/66 ,  H01L23/522 ,  H01L23/532

Abstract: In certain aspects of the disclosure, a cell includes a first dummy gate extended along a second lateral direction and on a boundary of the cell, a second dummy gate extended along the second lateral direction and on an opposite boundary of the cell, and a third gate extended along the second lateral direction, wherein the third gate is between the first dummy gate and the second dummy gate. The cell also includes a source between the second dummy gate and the third gate electrically coupled to a power rail. The cell further includes a metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction and above the first dummy gate, the source, and the third gate, wherein the metal interconnect is configured to couple the first dummy gate to the power rail through the source.

公开(公告)号：US20170365657A1

公开(公告)日：2017-12-21

申请号：US15186326

申请日：2016-06-17

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong CHEN ,  Hyeokjin Bruce LIM ,  Satyanarayana SAHU ,  Venugopal BOYNAPALLI

IPC: H01L29/06 ,  H01L27/02 ,  H01L23/535

CPC classification number: H01L29/0646 ,  H01L23/528 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875

Abstract: A MOS IC may include a first contact interconnect in a first standard cell that extends in a first direction and contacts a first MOS transistor source and a voltage source. Still further, the MOS IC may include a first double diffusion break extending along a first boundary in the first direction of the first standard cell and a second standard cell. The MOS IC may also include a second contact interconnect extending over a portion of the first double diffusion break. In an aspect, the second contact interconnect may be within both the first standard cell and the second standard cell and coupled to the voltage source. Additionally, the MOS IC may include a third contact interconnect extending in a second direction orthogonal to the first direction and couples the first contact interconnect and the second contact interconnect together.

公开(公告)号：US20240322819A1

公开(公告)日：2024-09-26

申请号：US18188656

申请日：2023-03-23

Applicant: QUALCOMM Incorporated

Inventor： Giby SAMSON ,  Ramaprasath VILANGUDIPITCHAI ,  Pavan Kumar PATIBANDA ,  Joshua ONG ,  Chethan SWAMYNATHAN ,  Vajram GHANTASALA ,  Venugopal BOYNAPALLI ,  Madan KRISHNAPPA ,  Vineet OORAMKUMARATH ,  Mohamed Saud MUSLIYARAKATH

IPC: H03K17/687 ,  H03K3/012 ,  H03K3/3562

CPC classification number: H03K17/6872 ,  H03K3/012 ,  H03K3/35625

Abstract: Aspects of the present disclosure provide cells including integrated switches and/or integrated clamps. In some aspects, a cell includes a circuit having an input and an output, and a switch coupled between a supply rail and the circuit, wherein the switch is configured to receive an enable signal, turn on when the enable signal has a first logic value, and turn off when the enable signal has a second logic value. The cell also includes a first clamp coupled to the output of the circuit, wherein the first clamp is configured to clamp the output of the circuit when the enable signal has the second logic value.

公开(公告)号：US20210280571A1

公开(公告)日：2021-09-09

申请号：US16808336

申请日：2020-03-03

Applicant: QUALCOMM Incorporated

Inventor： Hyeokjin LIM ,  Bharani CHAVA ,  Foua VANG ,  Seung Hyuk KANG ,  Venugopal BOYNAPALLI

IPC: H01L27/02 ,  H01L23/528 ,  H03K19/0185

Abstract: A MOS IC logic cell includes a plurality of gate interconnects extending on tracks in a first direction. The logic cell includes intra-cell routing interconnects coupled to at least a subset of the gate interconnects. The intra-cell routing interconnects include intra-cell Mx layer interconnects on an Mx layer extending in the first direction. The Mx layer is a lowest metal layer for PG extending in the first direction. The intra-cell Mx layer interconnects extend in the first direction over at least a subset of the tracks excluding every mth track, where 2≤m m*P