公开(公告)号：US10833017B2

公开(公告)日：2020-11-10

申请号：US15352342

申请日：2016-11-15

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Haining Yang ,  Youseok Suh ,  Jihong Choi ,  Junjing Bao

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532

Abstract: A semiconductor device may include a source/drain contact trench adjacent to a gate. The source/drain contact trench may include a first portion and a second portion on the first portion. The semiconductor device also may include an insulating contact spacer liner within the source/drain contact trench. The insulating contact spacer liner contacts the first portion but not the second portion of the source/drain contact trench. The semiconductor device may further include a conductive material within the insulating contact spacer liner and the second portion of the source/drain contact trench. The conductive material may land in a source/drain region of the semiconductor device.

公开(公告)号：US10090305B2

公开(公告)日：2018-10-02

申请号：US15197949

申请日：2016-06-30

Applicant: QUALCOMM Incorporated

Inventor： Jun Yuan ,  Yanxiang Liu ,  Kern Rim

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/28 ,  H01L29/49

Abstract: Fin Field Effect Transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits with single and double diffusion breaks for increased performance are disclosed. In one aspect, a FinFET CMOS circuit employing single and double diffusion breaks includes a P-type FinFET that includes a first Fin formed from a semiconductor substrate and corresponding to a P-type diffusion region. The FinFET CMOS circuit includes an N-type FinFET that includes a second Fin formed from the semiconductor substrate and corresponding to an N-type diffusion region. To electrically isolate the P-type FinFET, first and second single diffusion break (SDB) isolation structures are formed in the first Fin on either side of a gate of the P-type FinFET. To electrically isolate the N-type FinFET, first and second double diffusion break (DDB) isolation structures are formed in the second Fin on either side of a gate of the N-type FinFET.

公开(公告)号：US20180006035A1

公开(公告)日：2018-01-04

申请号：US15197949

申请日：2016-06-30

Applicant: QUALCOMM Incorporated

Inventor： Jun Yuan ,  Yanxiang Liu ,  Kern Rim

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L21/28 ,  H01L21/02 ,  H01L21/762 ,  H01L21/306 ,  H01L29/49 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/02164 ,  H01L21/28035 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/7846

Abstract: Fin Field Effect Transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits with single and double diffusion breaks for increased performance are disclosed. In one aspect, a FinFET CMOS circuit employing single and double diffusion breaks includes a P-type FinFET that includes a first Fin formed from a semiconductor substrate and corresponding to a P-type diffusion region. The FinFET CMOS circuit includes an N-type FinFET that includes a second Fin formed from the semiconductor substrate and corresponding to an N-type diffusion region. To electrically isolate the P-type FinFET, first and second single diffusion break (SDB) isolation structures are formed in the first Fin on either side of a gate of the P-type FinFET. To electrically isolate the N-type FinFET, first and second double diffusion break (DDB) isolation structures are formed in the second Fin on either side of a gate of the N-type FinFET.

公开(公告)号：US20160225767A1

公开(公告)日：2016-08-04

申请号：US14611090

申请日：2015-01-30

Applicant: QUALCOMM INCORPORATED

Inventor： Yanxiang Liu ,  Stanley Seungchul Song

IPC: H01L27/092 ,  H01L29/08 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/0207 ,  H01L29/0847

Abstract: A semiconductor device includes a diffusion area, a gate structure coupled to the diffusion area, and a dummy gate structure coupled to the diffusion area. The gate structure extends a first distance beyond the diffusion area, and the dummy gate structure extends a second distance beyond the diffusion area.

Abstract translation: 半导体器件包括扩散区域，耦合到扩散区域的栅极结构以及耦合到扩散区域的虚拟栅极结构。 栅极结构延伸超过扩散区域的第一距离，并且虚拟栅极结构延伸超过扩散区域的第二距离。

公开(公告)号：US10141306B2

公开(公告)日：2018-11-27

申请号：US15418651

申请日：2017-01-27

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Haining Yang

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/3115 ,  H01L27/088 ,  H01L29/06 ,  H01L21/308 ,  H01L21/306 ,  H01L29/66

Abstract: To avoid the problems associated with low density spin on dielectrics, some examples of the disclosure include a finFET with an oxide material having different densities. For example, one such finFET may include an oxide material located in a gap between adjacent fins, the oxide material directly contacts the adjacent fins of the plurality of fins with a first density proximate to a top layer of the oxide material and a second density proximate to a bottom layer of the oxide material and wherein the first density is greater than the second density.

公开(公告)号：US20170309611A1

公开(公告)日：2017-10-26

申请号：US15133377

申请日：2016-04-20

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Haining Yang ,  Junjing Bao

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L27/0255 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/66128 ,  H01L29/66545 ,  H01L29/8611

Abstract: Aspects for forming a self-aligned single diffusion break (SDB) isolation structure in a gate region of a diode for reduced capacitance, resistance, and/or area are disclosed. In one aspect, a diode is provided that includes a semiconductor substrate having a well region. P-doped and N-doped diffusion regions are formed in the well region of the semiconductor substrate. A self-aligned SDB isolation structure is formed in and self-aligned with a gate region between the P-doped and N-doped diffusion regions that electrically isolates such regions. The self-aligned SDB isolation structure reduces the parasitic capacitance of the diode compared to diodes having conductive gate structures in the gate region. The self-aligned SDB isolation structure has a width that reduces the length of a discharge path compared to conventional diodes, which reduces on-state resistance of the diode.

公开(公告)号：US09537007B2

公开(公告)日：2017-01-03

申请号：US14680711

申请日：2015-04-07

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Yanxiang Liu

IPC: H01L21/70 ,  H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7845 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/1037 ,  H01L29/4232 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: A semiconductor fin includes a channel region. A gate-stressor member, formed of a metal, extends transverse to the fin and includes gate surfaces that straddle the fin in the channel region. The gate-stressor member has a configuration that includes a partial cut spaced from the fin by a cut distance. The configuration causes, through the gate surfaces, a transverse stress in the fin, having a magnitude that corresponds to the cut distance. Transverse stressor members, formed of a metal, straddle the fin at regions outside of the channel region and cause, at the regions outside of the channel region, additional transverse stresses in the fin. The magnitude that corresponds to the cut distance, in combination with the additional transverse stresses, induces a longitudinal compressive strain in the channel region.

Abstract translation: 半导体鳍片包括沟道区域。 由金属形成的闸应力部件横向于翅片延伸并且包括在通道区域中跨过翅片的门表面。 闸门应力器构件具有包括与翅片间隔开切割距离的部分切割的构造。 该结构通过栅极表面导致鳍中的横向应力，其具有对应于切割距离的大小。 由金属形成的横向应力器构件在通道区域外的区域跨越翅片，并且在通道区域外的区域处引起翅片中额外的横向应力。 对应于切割距离的大小与附加的横向应力相结合，在通道区域中引起纵向压缩应变。

公开(公告)号：US10134734B2

公开(公告)日：2018-11-20

申请号：US15197949

申请日：2016-06-30

Applicant: QUALCOMM Incorporated

Inventor： Jun Yuan ,  Yanxiang Liu ,  Kern Rim

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/28 ,  H01L29/49

Abstract: Fin Field Effect Transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits with single and double diffusion breaks for increased performance are disclosed. In one aspect, a FinFET CMOS circuit employing single and double diffusion breaks includes a P-type FinFET that includes a first Fin formed from a semiconductor substrate and corresponding to a P-type diffusion region. The FinFET CMOS circuit includes an N-type FinFET that includes a second Fin formed from the semiconductor substrate and corresponding to an N-type diffusion region. To electrically isolate the P-type FinFET, first and second single diffusion break (SDB) isolation structures are formed in the first Fin on either side of a gate of the P-type FinFET. To electrically isolate the N-type FinFET, first and second double diffusion break (DDB) isolation structures are formed in the second Fin on either side of a gate of the N-type FinFET.

公开(公告)号：US10062763B2

公开(公告)日：2018-08-28

申请号：US14723199

申请日：2015-05-27

Applicant: QUALCOMM Incorporated

Inventor： Junjing Bao ,  Haining Yang ,  Yanxiang Liu ,  Jeffrey Junhao Xu

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/417

CPC classification number: H01L29/495 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/288 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A sacrificial cap is grown on an upper surface of a conductor. A dielectric spacer is against a side of the conductor. An upper dielectric side spacer is formed on a sidewall of the sacrificial cap. The sacrificial cap is selectively etched, leaving a cap recess, and the upper dielectric side spacer facing the cap recess. Silicon nitride is filled in the cap recess, to form a center cap and a protective cap having center cap and the upper dielectric spacer.

公开(公告)号：US10018515B2

公开(公告)日：2018-07-10

申请号：US14856004

申请日：2015-09-16

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Haining Yang ,  Kern Rim

IPC: G01K7/01 ,  H01L27/092 ,  H01L29/786

CPC classification number: G01K7/015 ,  H01L27/0251 ,  H01L27/0924 ,  H01L29/78606

Abstract: A device includes a source contact, a drain contact, a gate contact, and a body contact. The body contact is electrically coupled to a temperature sensing circuit. The source contact, the drain contact, the gate contact, and the body contact are included in a fin field-effect transistor (finFET).