公开(公告)号：US20230299048A1

公开(公告)日：2023-09-21

申请号：US17655394

申请日：2022-03-18

Applicant: QUALCOMM Incorporated

Inventor： Yangyang Sun ,  Stanley Seungchul Song ,  Lily Zhao

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/06586 ,  H01L2225/06541 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L24/14

Abstract: A three-dimensional (3D) integrated circuit (IC) (3DIC) package with a bottom die layer employing an interposer substrate, and related fabrication methods. To facilitate the ability to fabricate the 3DIC package using a top die-to-bottom wafer process, a bottom die layer of the 3DIC package includes an interposer substrate. This interposer substrate provides support for a bottom die(s) of the 3DIC package. The interposer substrate is extended in length to be longer in length than the top die. The interposer substrate provides additional die area in the bottom die layer in which a larger length, top die can be bonded. In this manner, the bottom die layer, with its extended interposer substrate, can be formed in a bottom wafer in which the top die can be bonded in a top die-to-bottom wafer fabrication process.

公开(公告)号：US20240421119A1

公开(公告)日：2024-12-19

申请号：US18336331

申请日：2023-06-16

Applicant: QUALCOMM Incorporated

Inventor： Yangyang Sun ,  Yue Li ,  Lily Zhao ,  Piyush Gupta ,  Xuefeng Zhang

IPC: H01L23/00

Abstract: Flexible under-bump metallization sizes and patterning, and related integrated circuit packages and fabrication methods are disclosed. First under-bump metallizations (UBMs) of a first, larger size and pitch are provided in the die and coupled to corresponding metal interconnects in the package substrate. One or more second UBMs of a second, reduced size UBMs can also be located in the core area of the die. This provides greater flexibility in the design and layout of the die, because different circuits within the die (e.g., I/O related circuits) may only require coupling to smaller size UBMs for performance requirements and thus can be more flexibility located in the die. Also, to further reduce pitch of the second, smaller size UBMs, one or more of the second, smaller size UBMs can be formed as oblong-shaped UBMs, which can still maintain a minimum separation based on metal interconnect pitch limitations in the package substrate.

公开(公告)号：US11694982B2

公开(公告)日：2023-07-04

申请号：US17185244

申请日：2021-02-25

Applicant: QUALCOMM Incorporated

Inventor： Wei Hu ,  Dongming He ,  Wen Yin ,  Zhe Guan ,  Lily Zhao

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/11013 ,  H01L2224/11622 ,  H01L2224/11849 ,  H01L2224/13147 ,  H01L2224/13584 ,  H01L2224/13655

Abstract: Disclosed are examples of integrated circuit (IC) structures and techniques to fabricate IC structures. Each IC package may include a die (e.g., a flip-chip (FC) die) and one or more die interconnects to electrically couple the die to a substrate. The die interconnect may include a pillar, a wetting barrier on the pillar, and a solder cap on the wetting barrier. The wetting barrier may be wider than the pillar. The die interconnect may also include a low wetting layer formed on the wetting barrier.

公开(公告)号：US20240371736A1

公开(公告)日：2024-11-07

申请号：US18310331

申请日：2023-05-01

Applicant: QUALCOMM Incorporated

Inventor： Omar James Bchir ,  Dongming He ,  Ryan Lane ,  Kuiwon Kang ,  Lily Zhao

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/48 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00

Abstract: Substrate employing core with cavity embedding reduced height electrical device(s), and related integrated circuit (IC) packages and fabrication methods are also disclosed. The cavity of the core (that has one or more core layers) of the substrate includes an embedded electrical device structure that an electrical device built upon another second component(s) to make the overall height of the electrical device structure compatible with the height of the cavity of the core. In this manner, the design criteria used to select thickness or height of the core for providing the desired stability in the substrate can be incompatible with the thickness or the height of the embedded electrical device.

公开(公告)号：US11557557B2

公开(公告)日：2023-01-17

申请号：US16917295

申请日：2020-06-30

Applicant: QUALCOMM Incorporated

Inventor： Yangyang Sun ,  Dongming He ,  Lily Zhao

IPC: H01L23/00

Abstract: Disclosed is a flip-chip device. The flip-chip device includes a die having a plurality of under bump metallizations (UBMs); and a package substrate having a plurality of bond pads. The plurality of UBMs include a first set of UBMs having a first size and a first minimum pitch and a second set of UBMs having a second size and a second minimum pitch. The first set of UBMs and the second set of UBMs are each electrically coupled to the package substrate by a bond-on-pad connection.

公开(公告)号：US20180331061A1

公开(公告)日：2018-11-15

申请号：US15843865

申请日：2017-12-15

Applicant: QUALCOMM Incorporated

Inventor： Dongming He ,  Lily Zhao ,  Wei Wang ,  Ahmer Syed

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L21/56

CPC classification number: H01L24/13 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/56 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/94 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/0221 ,  H01L2224/02215 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/03466 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13655 ,  H01L2224/16238 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/0544 ,  H01L2924/00012 ,  H01L2924/07025 ,  H01L2924/01028 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A device comprising a semiconductor die and a redistribution portion coupled to the semiconductor die. The redistribution portion includes a passivation layer and a redistribution interconnect comprising a first surface and a second surface opposite to the first surface. The redistribution interconnect is formed over the passivation layer such that the first surface is over the passivation layer and the second surface is free of contact with any passivation layer. The device includes a bump interconnect coupled to the second surface of the redistribution interconnect. In some implementations, the bump interconnect comprises a surface that faces the redistribution interconnect, and wherein an entire surface of the bump interconnect that faces the redistribution interconnect is free of contact with the passivation layer.

公开(公告)号：US12113038B2

公开(公告)日：2024-10-08

申请号：US17027316

申请日：2020-09-21

Applicant: QUALCOMM Incorporated

Inventor： Dongming He ,  Hung-Yuan Hsu ,  Yangyang Sun ,  Wei Hu ,  Wei Wang ,  Lily Zhao

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/13027 ,  H01L2924/35

Abstract: A thermal compression flip chip (TCFC) bump may be used for high performance products that benefit from a fine pitch. In one example, a new TCFC bump structure adds a metal pad underneath the TCFC copper pillar bump to cover the exposed aluminum bump pad. This new structure prevents the pad from corroding and reduces mechanical stress to the pad and underlying silicon dielectric layers enabling better quality and reliability and further bump size reduction. For example, a flip chip connection may include a substrate; a metal pad on a contact side of the substrate and a first passivation layer on the contact side of the substrate to protect the metal pad from corrosion.

公开(公告)号：US11948909B2

公开(公告)日：2024-04-02

申请号：US17574360

申请日：2022-01-12

Applicant: QUALCOMM Incorporated

Inventor： Yangyang Sun ,  Dongming He ,  Lily Zhao

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L24/73 ,  H01L24/26 ,  H01L24/32 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/30 ,  H01L24/33 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13082 ,  H01L2224/16148 ,  H01L2224/26125 ,  H01L2224/2919 ,  H01L2224/301 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/73253 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06565

Abstract: A package that includes a first integrated device comprising a first plurality of interconnects; a plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device comprising a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device through the second plurality of interconnects, the plurality of solder interconnects and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device.

公开(公告)号：US20240079352A1

公开(公告)日：2024-03-07

申请号：US17929408

申请日：2022-09-02

Applicant: QUALCOMM Incorporated

Inventor： Jihong Choi ,  Giridhar Nallapati ,  Lily Zhao ,  Dongming He

IPC: H01L23/64 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01L23/642 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/16235 ,  H01L2224/17163 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/19041 ,  H01L2924/30101 ,  H01L2924/30105 ,  H01L2924/30107

Abstract: Aspects disclosed herein include integrated circuit (IC) packages employing a capacitor interposer substrate with aligned external interconnects, and related fabrication methods. The IC package includes one or more semiconductor dies (“dies”) electrically coupled to a package substrate that supports electrical signal routing to and from the die(s). The capacitor interposer substrate is disposed between the die(s) and the package substrate. The die(s) is coupled to embedded capacitor(s) in the capacitor interposer substrate through die interconnects coupled to external interconnects of the capacitor interposer substrate. In exemplary aspects, the external interconnects on the outer surfaces of the capacitor interposer substrate are aligned. In this manner, the capacitor interposer substrate can maintain interconnect compatibility to the die(s) and package substrate if the die(s) and package substrate have a pattern of die interconnects and external interconnects that are designed to align with each other when coupled to each other.

公开(公告)号：US08847391B2

公开(公告)日：2014-09-30

申请号：US13777271

申请日：2013-02-26

Applicant: QUALCOMM Incorporated

Inventor： Zhongping Bao ,  Lily Zhao ,  Michael Kim-Kwong Han

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06133 ,  H01L2224/06141 ,  H01L2224/06145 ,  H01L2224/06517 ,  H01L2224/13006 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/14145 ,  H01L2224/811 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/2064

Abstract: Some exemplary embodiments of this disclosure pertain to a semiconductor package that includes a packaging substrate, a die and a set of under bump metallization (UBM) structures coupled to the packaging substrate and the die. Each UBM structure has a non-circular cross-section along its respective lateral dimension. Each UBM structure includes a first narrower portion and a second wider portion. The first narrower portion has a first width. The second wider portion has a second width that is greater than the first width. Each UBM structure is oriented towards a particular region of the die such that the first narrower portion of the UBM structure is closer than the second wider portion of the UBM structure to the particular region of the die.

Abstract translation: 本公开的一些示例性实施例涉及包括封装衬底，管芯和耦合到封装衬底和管芯的一组凹凸金属化（UBM）结构的半导体封装。 每个UBM结构沿其相应的横向尺寸具有非圆形横截面。 每个UBM结构包括第一较窄部分和第二较宽部分。 第一较窄部分具有第一宽度。 第二较宽部分具有大于第一宽度的第二宽度。 每个UBM结构朝向模具的特定区域，使得UBM结构的第一较窄部分比UBM结构的第二较宽部分更靠近模具的特定区域。