公开(公告)号：US20240431092A1

公开(公告)日：2024-12-26

申请号：US18338440

申请日：2023-06-21

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Wilfred Gomes ,  Tahir Ghani ,  Anand S. Murthy

IPC: H10B12/00

Abstract: A transistor may include a source region, a drain region, a channel region between the source region and the drain region in a first direction, a gate electrode, a source contact, and a drain contact. A first portion of the gate electrode is over the channel region in a second direction substantially perpendicular to the first direction. A second portion of the gate electrode is over a first portion of the drain region in the second direction. The source contact is over at least part of the source region. The drain contact is over a second portion of the drain region. A distance from an edge of the first portion of the drain region to an edge of the gate electrode or to an edge the first trench electrode in the first direction is greater than a fourth of a length of the gate electrode in the first direction.

公开(公告)号：US12170273B2

公开(公告)日：2024-12-17

申请号：US17210682

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Sanka Ganesan ,  Abhishek A. Sharma ,  Doug B. Ingerly ,  Mauro J. Kobrinsky ,  Kevin Fischer

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/12 ,  H01L23/528 ,  H01L23/538 ,  H01L25/065

Abstract: Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages, related to direct chip attach of dies and circuit boards. An example microelectronic assembly includes a die with IC components provided over the die's frontside, and a metallization stack provided over the die's backside. The die further includes die interconnects extending between the frontside and the backside of the die, to electrically couple the IC components and the metallization stack. The assembly further includes backside conductive contacts, provided over the side of the metallization stack facing away from the die, the backside conductive contacts configured to route signals to/from the IC components via the metallization stack and the die interconnects, and configured to be coupled to respective conductive contacts of a circuit board in absence of a package substrate between the die and the circuit board.

公开(公告)号：US20240222326A1

公开(公告)日：2024-07-04

申请号：US18148528

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Wilfred Gomes ,  Nisha Ananthakrishnan ,  Kemal Aygun ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H10B10/00 ,  H10B12/00 ,  H10B80/00

CPC classification number: H01L25/0655 ,  H01L23/5226 ,  H01L23/5283 ,  H10B10/12 ,  H10B12/37 ,  H10B80/00

Abstract: Embodiments of a microelectronic assembly include: a first integrated circuit (IC) die having a first memory circuit and a second memory circuit; a second IC die; a third IC die; and a package substrate. The first IC die is between the second IC die and the package substrate. The first IC die comprises: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. The first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.

公开(公告)号：US11984430B2

公开(公告)日：2024-05-14

申请号：US18128958

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Mark T. Bohr ,  Wilfred Gomes ,  Rajesh Kumar ,  Pooya Tadayon ,  Doug Ingerly

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/13 ,  H01L2225/06541

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

公开(公告)号：US20240006415A1

公开(公告)日：2024-01-04

申请号：US17856885

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Wilfred Gomes ,  Tahir Ghani ,  Anand Murthy

IPC: H01L27/092 ,  H01L23/473 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L23/473 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78696 ,  H01L29/775 ,  H01L21/02603 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/66742 ,  H01L29/66439

Abstract: Techniques and mechanisms for providing an integrated circuit (IC) which comprises an interconnect that extends between channel structures of two transistors. In an embodiment, a separation layer is provided between a first stack of channel structures and a second stack of channel structures, wherein an interior region of the separation layer comprises a sacrificial material which spans on overlap region between the stacks. Fabrication processes form a hole which exposes the interior region, and etching is performed to remove the sacrificial material from the separation layer. Subsequently, deposition processing forms in the interior region a trace portion of the interconnect. In another embodiment, the interconnect comprises a contiguous body of a conductor material, wherein the contiguous body extends to form respective regions of the trace portion, and a via portion of the interconnect.

公开(公告)号：US20240004129A1

公开(公告)日：2024-01-04

申请号：US17853732

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Debendra Mallik ,  John Heck ,  Pushkar Sharad Ranade ,  Ravindranath Vithal Mahajan ,  Thomas Liljeberg ,  Wilfred Gomes ,  Abhishek A. Sharma ,  Tahir Ghani

IPC: G02B6/12 ,  G02B6/13 ,  H01L25/16 ,  H01L23/00

CPC classification number: G02B6/12002 ,  G02B6/12004 ,  G02B6/13 ,  H01L25/167 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in an array; and a plurality of photonic integrated circuit (PIC) dies, each PIC die having waveguides. Adjacent microelectronic sub-assemblies are coupled to one of the PIC dies by interconnects such that any one PIC die is coupled to more than two adjacent microelectronic sub-assemblies, and the microelectronic sub-assemblies coupled to each PIC die in the plurality of PIC dies are communicatively coupled by the waveguides in the PIC die. Each microelectronic sub-assembly comprises: an interposer integrated circuit (IC) die comprising one or more electrical controller circuit proximate to at least one edge of the interposer IC die; a first plurality of IC dies coupled to a first surface of the interposer IC die; and a second plurality of IC dies coupled to an opposing second surface of the interposer IC die.

公开(公告)号：US20230410907A1

公开(公告)日：2023-12-21

申请号：US18312867

申请日：2023-05-05

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Sagar Suthram ,  Tahir Ghani ,  Wilfred Gomes ,  Anand S. Murthy

IPC: G11C16/04 ,  H10B43/27 ,  G11C16/26 ,  G11C16/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/778 ,  H01L29/423 ,  H01L29/786

CPC classification number: G11C16/0483 ,  H10B43/27 ,  G11C16/26 ,  G11C16/10 ,  H01L29/78696 ,  H01L29/0665 ,  H01L29/778 ,  H01L29/42392 ,  H01L29/7851

Abstract: IC devices implementing 2T memory cells with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as an “angled transistor” if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. 2T memory cells with read and write transistors provided in different planes of an IC device, stacked substantially over one another, and having either the read transistors or the write transistors being angled transistors provide a promising way to increasing memory cell densities, drive current, and design flexibility in making electrical connections to, or between, various transistor terminals and control lines of memory arrays, thus providing good scalability in the number of 2T memory cells included in memory arrays.

公开(公告)号：US20230395676A1

公开(公告)日：2023-12-07

申请号：US17829706

申请日：2022-06-01

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Abhishek A. Sharma ,  Wilfred Gomes ,  Tahir Ghani ,  Anand S. Murthy ,  Pushkar Sharad Ranade

IPC: H01L29/423 ,  H01L29/06 ,  H01L27/092

CPC classification number: H01L29/4238 ,  H01L29/0665 ,  H01L29/42392 ,  H01L27/092

Abstract: IC devices with transistors having angled gates, and related assemblies and methods, are disclosed herein. A transistor is referred to as having an “angled gate” if an angle between a projection of the gate of the transistor onto a plane of a support structure (e.g., a die) over which the transistor is implemented and an analogous projection of a longitudinal axis of an elongated structure (e.g., a fin or a nanoribbon having one or more semiconductor materials) based on which the transistor is built is between 10 degrees and 80 degrees. Transistors having angled gates provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips and/or decreasing short-channel effects associated with continuous scaling of IC components.

公开(公告)号：US11830829B2

公开(公告)日：2023-11-28

申请号：US17836117

申请日：2022-06-09

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mark Bohr ,  Doug Ingerly ,  Rajesh Kumar ,  Harish Krishnamurthy ,  Nachiket Venkappayya Desai

IPC: H01L23/64 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/645 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06558 ,  H01L2225/06582 ,  H01L2924/19042

Abstract: Techniques and mechanisms for providing an inductor with an integrated circuit (IC) die. In an embodiment, the IC die comprises integrated circuitry and one or more first metallization layers. The IC die is configured to couple to a circuit device including one or more second metallization layers, where such coupling results in the formation of an inductor which is coupled to the integrated circuitry. One or more loop structures of the inductor each span both some or all of the one or more first metallization layers and some or all of the one or more second metallization layers. In another embodiment, the IC die or the circuit device includes a ferromagnetic material to concentrate a magnetic flux which is provided with the inductor.

公开(公告)号：US11817442B2

公开(公告)日：2023-11-14

申请号：US17114700

申请日：2020-12-08

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Abhishek A. Sharma ,  Mauro J. Kobrinsky ,  Doug B. Ingerly

IPC: H01L25/18 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L23/532

CPC classification number: H01L25/18 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2224/08145 ,  H01L2224/08501 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32501 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01014

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.