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公开(公告)号：US12052873B2
公开(公告)日：2024-07-30
申请号：US16989430
申请日：2020-08-10
Applicant: Intel Corporation
Inventor： Dmitri E. Nikonov , Clifford Lu Ong , Ian A. Young
IPC: H10B51/20 , G06N3/063 , G11C11/54 , H01L25/065 , H01L29/06 , H01L29/423 , H01L29/78 , H01L29/786 , H10B51/30 , H10B51/40
CPC classification number: H10B51/20 , G06N3/063 , G11C11/54 , H01L25/0657 , H01L29/0673 , H01L29/42392 , H01L29/78391 , H01L29/7851 , H01L29/78696 , H10B51/30 , H10B51/40 , H01L2225/06506
Abstract: Disclosed herein are neural computing dies with stacked neural core regions as well as related methods and assemblies. In some embodiments, a neural computing die may include: a first neural core region; a second neural core region; and an inter-core interconnect region in a volume between the first neural core region and the second neural core region, wherein the inter-core interconnect region includes a conductive pathway between the first neural core region and the second neural core region, and the conductive pathway includes a conductive via.
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公开(公告)号：US12009018B2
公开(公告)日：2024-06-11
申请号：US17839345
申请日：2022-06-13
Applicant: Intel Corporation
Inventor： Chia-Ching Lin , Sasikanth Manipatruni , Tanay Gosavi , Dmitri Nikonov , Benjamin Buford , Kaan Oguz , John J. Plombon , Ian A. Young
CPC classification number: G11C11/161 , H10N50/80 , H10N50/85
Abstract: An apparatus is provided which comprises: a stack comprising a magnetic insulating material (MI such as EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene), wherein the magnetic insulating material has a first magnetization; a magnet with a second magnetization, wherein the magnet is adjacent to the TMD of the stack; and an interconnect comprising a spin orbit material, wherein the interconnect is adjacent to the magnet.
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公开(公告)号：US11664305B2
公开(公告)日：2023-05-30
申请号：US16455662
申请日：2019-06-27
Applicant: Intel Corporation
Inventor： Kevin Lai Lin , Manish Chandhok , Miriam Reshotko , Christopher Jezewski , Eungnak Han , Gurpreet Singh , Sarah Atanasov , Ian A. Young
IPC: H01L23/522 , H01L21/768 , H01L23/528
CPC classification number: H01L23/5222 , H01L21/76802 , H01L23/528 , H01L23/5226
Abstract: An interconnect structure is disclosed. The interconnect structure includes a first line of interconnects and a second line of interconnects. The first line of interconnects and the second line of interconnects are staggered. The individual interconnects of the second line of interconnects are laterally offset from individual interconnects of the first line of interconnects. A dielectric material is adjacent to at least a portion of the individual interconnects of at least one of the first line of interconnects and the second line of interconnects.
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公开(公告)号：US11495596B2
公开(公告)日：2022-11-08
申请号：US16147512
申请日：2018-09-28
Applicant: Intel Corporation
Inventor： Uygar E. Avci , Daniel H. Morris , Ian A. Young
Abstract: An integrated circuit structure comprises a substrate having a memory region of and an adjacent logic region. A first N type well (Nwell) is formed in the substrate for the memory region and a second Nwell formed in the substrate for the logic region. A plurality of memory transistors in the memory region and a plurality of logic transistors are in the logic region, wherein ones the memory transistors include a floating gate over a channel, and a source and a drain on opposite sides of the channel. A diode portion is formed over one of the source and the drain of at least one of the memory transistors to conduct charge to the floating-gate of the at least one of the memory transistors for state retention during power gating.
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公开(公告)号：US20220310147A1
公开(公告)日：2022-09-29
申请号：US17839345
申请日：2022-06-13
Applicant: Intel Corporation
Inventor： Chia-Ching Lin , Sasikanth Manipatruni , Tanay Gosavi , Dmitri Nikonov , Benjamin Buford , Kaan Oguz , John J. Plombon , Ian A. Young
Abstract: An apparatus is provided which comprises: a stack comprising a magnetic insulating material (MI such as EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene), wherein the magnetic insulating material has a first magnetization; a magnet with a second magnetization, wherein the magnet is adjacent to the TMD of the stack; and an interconnect comprising a spin orbit material, wherein the interconnect is adjacent to the magnet.
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Patent Agency Ranking
公开(公告)号：US20220123206A1
公开(公告)日：2022-04-21
申请号：US17565106
申请日：2021-12-29
Applicant: Intel Corporation
Inventor： Chia-Ching Lin , Sasikanth Manipatruni , Tanay Gosavi , Dmitri Nikonov , Benjamin Buford , Kaan Oguz , John J. Plombon , Ian A. Young
Abstract: An apparatus is provided which comprises: a stack comprising a magnetoelectric (ME such as BiFeO3, (LaBi)FeO3, LuFeO3, PMN-PT, PZT, AlN, SmBiFeO3, Cr2O3, etc.) material and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, graphene, etc.); a magnet adjacent to a first portion of the TMD of the stack; a first interconnect adjacent to the magnet; a second interconnect adjacent to the ME material of the stack; and a third interconnect adjacent to a second portion of the TMD of the stack.
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公开(公告)号：US11138499B2
公开(公告)日：2021-10-05
申请号：US16147176
申请日：2018-09-28
Applicant: Intel Corporation
Inventor： Abhishek Sharma , Jack T. Kavalieros , Ian A. Young , Sasikanth Manipatruni , Ram Krishnamurthy , Uygar Avci , Gregory K. Chen , Amrita Mathuriya , Raghavan Kumar , Phil Knag , Huseyin Ekin Sumbul , Nazila Haratipour , Van H. Le
IPC: G06N3/063 , H01L27/108 , H01L27/11502 , G06N3/04 , G06F17/16 , H01L27/11 , G11C11/54 , G11C7/10 , G11C11/419 , G11C11/409 , G11C11/22
Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.
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公开(公告)号：US11114144B2
公开(公告)日：2021-09-07
申请号：US16464260
申请日：2016-12-23
Applicant: Intel Corporation
Inventor： Sasikanth Manipatruni , Dmitri E. Nikonov , Ian A. Young
Abstract: An apparatus is provided which comprises: a first paramagnet; a stack of layers, a portion of which is adjacent to the first paramagnet, wherein the stack of layers is to provide an inverse Rashba-Edelstein effect; a second paramagnet; a magnetoelectric layer adjacent to the second paramagnet; and a conductor coupled to at least a portion of the stack of layers and the magnetoelectric layer.
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公开(公告)号：US11061646B2
公开(公告)日：2021-07-13
申请号：US16147004
申请日：2018-09-28
Applicant: Intel Corporation
Inventor： Huseyin Ekin Sumbul , Phil Knag , Gregory K. Chen , Raghavan Kumar , Abhishek Sharma , Sasikanth Manipatruni , Amrita Mathuriya , Ram Krishnamurthy , Ian A. Young
IPC: G06F7/544 , G11C8/10 , G11C8/08 , G11C7/12 , G11C11/4094 , G11C7/10 , G11C11/56 , G11C11/4091 , G06G7/16 , G11C11/419
Abstract: Compute-in memory circuits and techniques are described. In one example, a memory device includes an array of memory cells, the array including multiple sub-arrays. Each of the sub-arrays receives a different voltage. The memory device also includes capacitors coupled with conductive access lines of each of the multiple sub-arrays and circuitry coupled with the capacitors, to share charge between the capacitors in response to a signal. In one example, computing device, such as a machine learning accelerator, includes a first memory array and a second memory array. The computing device also includes an analog processor circuit coupled with the first and second memory arrays to receive first analog input voltages from the first memory array and second analog input voltages from the second memory array and perform one or more operations on the first and second analog input voltages, and output an analog output voltage.
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公开(公告)号：US11037614B2
公开(公告)日：2021-06-15
申请号：US16615780
申请日：2018-07-23
Applicant: Intel Corporation
Inventor： Huichu Liu , Sasikanth Manipatruni , Ian A. Young , Tanay Karnik , Daniel H. Morris , Kaushik Vaidyanathan
IPC: G11C11/22 , H01L27/11507 , H01L49/02
Abstract: Described is an apparatus to reduce or eliminate imprint charge, wherein the apparatus which comprises: a source line; a bit-line; a memory bit-cell coupled to the source line and the bit-line; a first multiplexer coupled to the bit-line; a second multiplexer coupled to the source-line; a first driver coupled to the first multiplexer; a second driver coupled to the second multiplexer; and a current source coupled to the first and second drivers.
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