Invention Grant
- Patent Title: Staggered lines for interconnect performance improvement and processes for forming such
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Application No.: US16455662Application Date: 2019-06-27
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Publication No.: US11664305B2Publication Date: 2023-05-30
- Inventor: Kevin Lai Lin , Manish Chandhok , Miriam Reshotko , Christopher Jezewski , Eungnak Han , Gurpreet Singh , Sarah Atanasov , Ian A. Young
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/768 ; H01L23/528

Abstract:
An interconnect structure is disclosed. The interconnect structure includes a first line of interconnects and a second line of interconnects. The first line of interconnects and the second line of interconnects are staggered. The individual interconnects of the second line of interconnects are laterally offset from individual interconnects of the first line of interconnects. A dielectric material is adjacent to at least a portion of the individual interconnects of at least one of the first line of interconnects and the second line of interconnects.
Public/Granted literature
- US3121973A Soil treating method Public/Granted day:1964-02-25
Information query
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