公开(公告)号：US20230093450A1

公开(公告)日：2023-03-23

申请号：US18072457

申请日：2022-11-30

Applicant: Applied Materials, Inc.

Inventor： Tzu-shun YANG ,  Rui CHENG ,  Karthik JANAKIRAMAN ,  Zubin HUANG ,  Diwakar KEDLAYA ,  Meenakshi GUPTA ,  Srinivas GUGGILLA ,  Yung-chen LIN ,  Hidetaka OSHIO ,  Chao LI ,  Gene LEE

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3213

Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.

公开(公告)号：US20210040617A1

公开(公告)日：2021-02-11

申请号：US16980325

申请日：2019-03-13

Applicant: Applied Materials, Inc.

Inventor： Zubin HUANG ,  Rui CHENG ,  Chen-An CHEN ,  Karthik JANAKIRAMAN

IPC: C23C16/50 ,  C23C16/24 ,  C23C16/455

Abstract: Method for depositing amorphous silicon materials are provide and include generating a plasma within a plasma unit in fluid communication with a process chamber and flowing the plasma through an ion suppressor to produce an activated fluid containing reactive species and neutral species. The activated fluid either contains no ions or contains a lower concentration of ions than the plasma. The method further includes flowing the activated fluid into a first inlet of a dual channel showerhead within the process chamber and flowing a silicon precursor into a second inlet of the dual channel showerhead. Thereafter, the method includes flowing a mixture of the activated fluid and the silicon precursor out of the dual channel showerhead and forming an amorphous silicon layer on a substrate disposed in the process chamber.

公开(公告)号：US20200266052A1

公开(公告)日：2020-08-20

申请号：US16795191

申请日：2020-02-19

Applicant: Applied Materials, Inc.

Inventor： Krishna NITTALA ,  Rui CHENG ,  Karthik JANAKIRAMAN ,  Praket Prakash JHA ,  Jinrui GUO ,  Jingmei LIANG

IPC: H01L21/02

Abstract: Aspects of the disclosure provide a method including depositing an underlayer comprising silicon oxide over a substrate, depositing a polysilicon liner on the underlayer, and depositing an amorphous silicon layer on the polysilicon liner. Aspects of the disclosure provide a device intermediate including a substrate, an underlayer comprising silicon oxide formed over the substrate, a polysilicon liner disposed on the underlayer, and an amorphous silicon layer disposed on the polysilicon liner.

公开(公告)号：US20200211834A1

公开(公告)日：2020-07-02

申请号：US16725226

申请日：2019-12-23

Applicant: Applied Materials, Inc.

Inventor： Chuanxi YANG ,  Hang YU ,  Sanjay KAMATH ,  Deenesh PADHI ,  Honggun KIM ,  Euhngi LEE ,  Zubin HUANG ,  Diwakar N. KEDLAYA ,  Rui CHENG ,  Karthik JANAKIRAMAN

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/02 ,  C23C16/513

Abstract: Methods for forming the silicon boron nitride layer are provided. The method includes positioning a substrate on a pedestal in a process region within a process chamber, heating a pedestal retaining the substrate, and introducing a first flow of a first process gas and a second flow of a second process gas to the process region. The first flow of the first process gas contains silane, ammonia, helium, nitrogen, argon, and hydrogen. The second flow of the second process gas contains diborane and hydrogen. The method also includes forming a plasma concurrently with the first flow of the first process gas and the second flow of the second process gas to the process region and exposing the substrate to the first process gas, the second process gas, and the plasma to deposit the silicon boron nitride layer on the substrate.

公开(公告)号：US20190027362A1

公开(公告)日：2019-01-24

申请号：US15988771

申请日：2018-05-24

Applicant: Applied Materials, Inc.

Inventor： Rui CHENG ,  Yi YANG ,  Yihong CHEN ,  Karthik JANAKIRAMAN ,  Abhijit Basu MALLICK

IPC: H01L21/02

Abstract: In one implementation, a method of forming an amorphous silicon layer on a substrate in a processing chamber is provided. The method comprises depositing a predetermined thickness of a sacrificial dielectric layer over a substrate. The method further comprises forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate. The method further comprises performing a plasma treatment to the patterned features. The method further comprises depositing an amorphous silicon layer on the patterned features and the exposed upper surface of the substrate. The method further comprises selectively removing the amorphous silicon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the amorphous silicon layer.

公开(公告)号：US20180076042A1

公开(公告)日：2018-03-15

申请号：US15695269

申请日：2017-09-05

Applicant: Applied Materials, Inc.

Inventor： Rui CHENG ,  Ziqing DUAN ,  Milind GADRE ,  Praket P. JHA ,  Abhijit Basu MALLICK ,  Deenesh PADHI

IPC: H01L21/285 ,  H01L21/3205 ,  H01L21/02 ,  H01L21/3105 ,  C23C16/30

CPC classification number: H01L21/28525 ,  C23C16/045 ,  C23C16/24 ,  C23C16/30 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02488 ,  H01L21/02494 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/0337 ,  H01L21/3105 ,  H01L21/32055

Abstract: Implementations described herein generally relate to the fabrication of integrated circuits and particularly to the deposition of a boron-doped amorphous silicon layers on a semiconductor substrate. In one implementation, a method of forming a boron-doped amorphous silicon layer on a substrate is provided. The method comprises depositing a predetermined thickness of a sacrificial dielectric layer over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, depositing conformally a predetermined thickness of a boron-doped amorphous silicon layer on the patterned features and the exposed upper surface of the substrate and selectively removing the boron-doped amorphous silicon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the boron-doped amorphous silicon layer.

公开(公告)号：US20160293483A1

公开(公告)日：2016-10-06

申请号：US15083590

申请日：2016-03-29

Applicant: Applied Materials, Inc.

Inventor： Pramit MANNA ,  Rui CHENG ,  Kelvin CHAN ,  Abhijit Basu MALLICK

IPC: H01L21/768

CPC classification number: H01L21/76846 ,  C23C16/045 ,  C23C16/16 ,  C23C16/342 ,  C23C16/46 ,  H01L21/28556 ,  H01L21/76864 ,  H01L21/76877

Abstract: Implementations of the present disclosure generally relate to methods for forming thin films in high aspect ratio feature definitions. In one implementation, a method of processing a substrate in a process chamber is provided. The method comprises flowing a boron-containing precursor comprising a ligand into an interior processing volume of a process chamber, flowing a nitrogen-containing precursor comprising the ligand into the interior processing volume and thermally decomposing the boron-containing precursor and the nitrogen-containing precursor in the interior processing volume to deposit a boron nitride layer over at least one or more sidewalls and a bottom surface of a high aspect ratio feature definition formed in and below a surface of a dielectric layer on the substrate.

Abstract translation: 本公开的实施方式一般涉及用于在高纵横比特征定义中形成薄膜的方法。 在一个实施方案中，提供了处理室中的衬底的处理方法。 该方法包括将包含配体的含硼前体流入处理室的内部处理体积，将含有配体的含氮前体流入内部处理体积并热分解含硼前体和含氮前体 在内部处理体积中，在形成在基板上的电介质层的表面中和下方的高纵横比特征定义的至少一个或多个侧壁和底表面上沉积氮化硼层。

公开(公告)号：US20240304437A1

公开(公告)日：2024-09-12

申请号：US18650014

申请日：2024-04-29

Applicant: Applied Materials, Inc.

Inventor： Chuanxi YANG ,  Hang YU ,  Sanjay KAMATH ,  Deenesh PADHI ,  Honggun KIM ,  Euhngi LEE ,  Zubin HUANG ,  Diwakar N. KEDLAYA ,  Rui CHENG ,  Karthik JANAKIRAMAN

IPC: H01L21/02 ,  C23C16/02 ,  C23C16/34 ,  C23C16/513

CPC classification number: H01L21/0217 ,  C23C16/0209 ,  C23C16/345 ,  C23C16/513 ,  H01L21/02274

Abstract: Capacitor devices containing silicon boron nitride with high boron concentration are provided. In one or more examples, a capacitor device is provided and contains a stopper layer containing silicon boron nitride and disposed on a substrate, a dielectric layer disposed on the stopper layer, vias formed within the dielectric layer and the stopper layer, metal contacts disposed on bottoms of the vias, a nitride barrier layer containing a metal nitride material and disposed on walls of the vias and disposed on the metal contacts, and an oxide layer disposed within the vias on the nitride barrier layer, wherein the oxide layer contains one or more holes or voids formed therein. The silicon boron nitride contains about 18 atomic percent (at %) to about 50 at % of boron.

公开(公告)号：US20240035195A1

公开(公告)日：2024-02-01

申请号：US18226007

申请日：2023-07-25

Applicant: Applied Materials, Inc.

Inventor： Qinghua ZHAO ,  Rui CHENG ,  Dimitrios PAVLOPOULOS ,  Karthik JANAKIRAMAN

IPC: C30B25/16 ,  H01L21/02 ,  H01J37/32 ,  C30B29/06 ,  C30B29/52 ,  C30B25/10 ,  C23C16/06 ,  C23C16/24 ,  C23C16/46 ,  C23C16/507 ,  C23C16/52

CPC classification number: C30B25/165 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/0262 ,  H01J37/32816 ,  H01J37/32724 ,  H01J37/32449 ,  C30B29/06 ,  C30B29/52 ,  C30B25/10 ,  C23C16/06 ,  C23C16/24 ,  C23C16/46 ,  C23C16/507 ,  C23C16/52 ,  H01J2237/332 ,  H01J2237/2001 ,  H01J2237/182

Abstract: Embodiments of the present disclosure generally relate to methods, systems, and apparatus for forming layers having single crystalline structures. In one implementation, a method of processing substrates includes positioning a substrate in a processing volume of a chamber, and heating the substrate to a substrate temperature that is 800 degrees Celsius or less. The method includes maintaining the processing volume at a pressure within a range of 1.0 Torr to 8.0 Torr, and flowing one or more silicon-containing gases and one or more diluent gases into the processing volume. The method includes reacting the one or more silicon-containing gases to form one or more reactants, and depositing the one or more reactants onto an exposed surface of the substrate to form one or more silicon-containing layers on the exposed surface. The one or more silicon-containing layers each having a single crystalline structure.

公开(公告)号：US20220013359A1

公开(公告)日：2022-01-13

申请号：US17459839

申请日：2021-08-27

Applicant: Applied Materials, Inc.

Inventor： Takehito KOSHIZAWA ,  Rui CHENG ,  Tejinder SINGH ,  Hidetaka OSHIO

IPC: H01L21/033 ,  H01L21/311

Abstract: In an embodiment, a method for forming features for semiconductor processing. A first mandrel and a second mandrel are formed on a substrate. A first spacer is formed along a first sidewall of the first mandrel, and a second spacer is formed along a second sidewall of the second mandrel. A gap is defined between the first spacer and the second spacer. The gap is filled by a gap-filling material. In some examples, the gap-filling material includes a doped silicon material. In some examples, the first spacer and the second spacer each include a doped silicon material.