公开(公告)号：US11824761B1

公开(公告)日：2023-11-21

申请号：US16199744

申请日：2018-11-26

申请人： Xilinx, Inc.

发明人： Ben J. Jones

IPC分类号： H04L45/24 ,  H04L25/14 ,  H04L1/00

CPC分类号： H04L45/24 ,  H04L1/0045 ,  H04L25/14

摘要： Methods and apparatus for detecting alignment markers in received data streams received via a plurality of data lanes are disclosed. Corresponding data streams may be received via respective data lanes in the plurality of data lanes, where each data stream includes alignment markers delineating data frames, and each alignment marker has a predefined bit pattern. For each respective data lane, a determination is made whether a specified portion of the received data stream has at least a threshold degree of similarity with a portion of the predefined bit pattern. In response to determining, for one of the plurality of data lanes, that the specified portion has at least the threshold degree of similarity, a frame boundary may be determined based on the specified portion, and a verification may be performed, that the specified portion of the received data stream corresponds to an alignment marker.

公开(公告)号：US20230336266A1

公开(公告)日：2023-10-19

申请号：US18337934

申请日：2023-06-20

申请人： Kandou Labs, S.A.

发明人： Amin Shokrollahi ,  Ali Hormati ,  Roger Ulrich

IPC分类号： H04J13/00 ,  H04L25/03 ,  H04L25/02 ,  H04L25/14 ,  H04L25/49

CPC分类号： H04J13/004 ,  H04L25/03343 ,  H04L25/0272 ,  H04L25/0276 ,  H04L25/14 ,  H04L25/4919

摘要： An efficient communications apparatus is described for a vector signaling code to transport data and optionally a clocking signal between integrated circuit devices. Methods of designing such apparatus and their associated codes based on a new metric herein called the “ISI Ratio” are described which permit higher communications speed, lower system power consumption, and reduced implementation complexity.

公开(公告)号：US20230231647A1

公开(公告)日：2023-07-20

申请号：US18124127

申请日：2023-03-21

申请人： Entropic Communications, LLC

发明人： David Barr ,  Michail Tsatsanis ,  Arndt Mueller ,  Na Chen

IPC分类号： H04L1/00 ,  H04L12/28 ,  H04L25/14 ,  H04L47/70 ,  H04L1/02 ,  H04L5/00 ,  H03M13/11 ,  H03M13/00

CPC分类号： H04L1/0009 ,  H04L12/2801 ,  H04L12/2865 ,  H04L25/14 ,  H04L47/828 ,  H04L1/0042 ,  H04L1/02 ,  H04L5/0091 ,  H03M13/1102 ,  H03M13/618 ,  H04L1/0041 ,  H04L27/2602

摘要： A particular overall architecture for transmission over a bonded channel system consisting of two interconnected MoCA (Multimedia over Coax Alliance) 2.0 SoCs (Systems on a Chip) and a method and apparatus for the case of a “bonded” channel network. With a bonded channel network, the data is divided into two segments, the first of which is transported over a primary channel and the second of which is transported over a secondary channel.

公开(公告)号：US20220182210A1

公开(公告)日：2022-06-09

申请号：US17676972

申请日：2022-02-22

申请人： SONY GROUP CORPORATION

发明人： KAZUAKI TOBA ,  GEN ICHIMURA

IPC分类号： H04L5/02 ,  G09G5/00 ,  H04L9/08 ,  H04L25/02 ,  H04N21/4363 ,  H04N21/436 ,  H04L5/22 ,  H04L25/14 ,  H04N5/44

摘要： A signal is transmitted at a high speed in a direction opposite to a transmitting direction of a main large-capacity channel. A first transmitting unit transmits a first signal including a clock component to an external device through a transmission path as a differential signal. A second transmitting unit superimposes a second signal including a clock component on the transmission path as an in-phase signal to transmit to the external device. A state notifying unit communicates with the external device through a pair of differential transmission paths included in the transmission path and notifies the external device of a connection state of its own device by a DC bias potential of at least one of the pair of differential transmission paths.

公开(公告)号：US20220173883A1

公开(公告)日：2022-06-02

申请号：US17672410

申请日：2022-02-15

申请人： Kandou Labs, S.A.

发明人： Roger Ulrich ,  Armin Tajalli ,  Ali Hormati ,  Richard Simpson

IPC分类号： H04L7/00 ,  H04L25/14 ,  H04L7/033 ,  H04L25/49 ,  H04L25/03

摘要： Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

公开(公告)号：US11271706B2

公开(公告)日：2022-03-08

申请号：US17022356

申请日：2020-09-16

申请人： SONY CORPORATION

发明人： Kazuaki Toba ,  Gen Ichimura

IPC分类号： H04L5/02 ,  G09G5/00 ,  H04L9/08 ,  H04L25/02 ,  H04N21/4363 ,  H04N21/436 ,  H04L5/22 ,  H04L25/14 ,  H04N5/44

摘要： A signal is transmitted at a high speed in a direction opposite to a transmitting direction of a main large-capacity channel. A first transmitting unit transmits a first signal including a clock component to an external device through a transmission path as a differential signal. A second transmitting unit superimposes a second signal including a clock component on the transmission path as an in-phase signal to transmit to the external device. A state notifying unit communicates with the external device through a pair of differential transmission paths included in the transmission path and notifies the external device of a connection state of its own device by a DC bias potential of at least one of the pair of differential transmission paths.

公开(公告)号：US11245402B2

公开(公告)日：2022-02-08

申请号：US17327512

申请日：2021-05-21

申请人： Kandou Labs SA

发明人： Armin Tajalli

IPC分类号： H03L7/08 ,  H03L7/087 ,  H03L7/099 ,  H04L7/033 ,  H04L25/14 ,  H04L25/02 ,  H04L25/40 ,  H04L25/493 ,  H03K19/21 ,  H03L7/089 ,  H04L7/00

摘要： Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.

公开(公告)号：US20210288740A1

公开(公告)日：2021-09-16

申请号：US17336082

申请日：2021-06-01

申请人： Kandou Labs SA

发明人： Amin Shokrollahi ,  Ali Hormati ,  Roger Ulrich

IPC分类号： H04J13/00 ,  H04L25/03 ,  H04L25/02 ,  H04L25/14 ,  H04L25/49

摘要： An efficient communications apparatus is described for a vector signaling code to transport data and optionally a clocking signal between integrated circuit devices. Methods of designing such apparatus and their associated codes based on a new metric herein called the “ISI Ratio” are described which permit higher communications speed, lower system power consumption, and reduced implementation complexity.

公开(公告)号：US11032110B2

公开(公告)日：2021-06-08

申请号：US16808252

申请日：2020-03-03

申请人： Kandou Labs SA

发明人： Ali Hormati

IPC分类号： H04L25/02 ,  H04L25/49 ,  H04L25/08 ,  H04B3/14 ,  H04L25/14 ,  H04W72/04 ,  H04L25/03

摘要： Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.

公开(公告)号：US10956124B2

公开(公告)日：2021-03-23

申请号：US16356881

申请日：2019-03-18

申请人： VIAVI SOLUTIONS INC.

发明人： Reiner Schnizler

IPC分类号： G06F13/42 ,  G06F5/06 ,  G06F5/16 ,  H04L25/14 ,  H04L12/875

摘要： The disclosure relates to detecting phase slips that may occur in a multi-lane serial datalink. Phase slips may occur when a lane experiences lane skew, which may introduce a phase slip with respect to another lane. To detect phase slippage, the system may select a reference lane from among the lanes. The system may generate a pre-deskew delta value based on a difference between the FIFO filling level of the reference lane before a deskew and the FIFO filling level of a second lane before the deskew. The system may generate a post-deskew delta value based on a difference between the FIFO filling level of the reference lane after the deskew and the FIFO filling level of the second lane after the deskew. The system may use a difference between the post-deskew delta and the pre-deskew delta to detect phase slip on the second lane relative to the reference lane.