公开(公告)号：US11456389B2

公开(公告)日：2022-09-27

申请号：US16939022

申请日：2020-07-26

Applicant: Champion Microelectronic Corp. ,  Yutechnix, Inc.

Inventor： Haiping Dun ,  Hung-Chen Lin

IPC: H01L29/872 ,  H01L29/78 ,  H01L29/06 ,  H01L29/70

Abstract: Apparatus and other embodiments associated with high speed and high breakdown voltage MOS rectifier are disclosed. A Junction All Around structure, where a deep trench structure surrounds and encloses a P-N junction or a MOS structure, is created and applied in various rectifiers. In one embodiment, multiple deep trenches in concentric ring circles enclosed several horizontal P-N junctions in concentric ring circles. In another embodiment, an enclosed deep trench in ring circle surrounds a horizontal P-N junction, which results in a planar N-channel MOS during forward bias. This structure can be extended to multiple deep trenches with associated horizontal P-N junctions.

公开(公告)号：US20210225844A1

公开(公告)日：2021-07-22

申请号：US17207687

申请日：2021-03-21

Applicant: Zeno Semiconductor, Inc.

Inventor： Yuniarto Widjaja ,  Jin-Woo Han ,  Benjamin S. Louie

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/70 ,  G11C11/404 ,  H01L29/73 ,  G11C16/04 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/102 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36 ,  G11C16/26 ,  G11C16/34

Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

公开(公告)号：US10892354B2

公开(公告)日：2021-01-12

申请号：US16773031

申请日：2020-01-27

Applicant: Ideal Power, Inc.

Inventor： William C. Alexander ,  Richard A. Blanchard

IPC: H03K17/66 ,  H01L29/747 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/732 ,  H01L29/70

Abstract: Dual-base two-sided bipolar power transistors which use an insulated field plate to separate the emitter/collector diffusions from the nearest base contact diffusion. This provides a surprising improvement in turn-off performance, and in breakdown voltage.

公开(公告)号：US10770599B2

公开(公告)日：2020-09-08

申请号：US15853794

申请日：2017-12-23

Applicant: Yutechnix, Inc. ,  Champion Microelectronic Corp.

Inventor： Haiping Dun ,  Ho-Yuan Yu ,  Hung-Chen Lin

IPC: H01L29/872 ,  H01L29/78 ,  H01L29/06 ,  H01L29/70

Abstract: Apparatus and other embodiments associated with high speed and high breakdown voltage rectifier are disclosed. A Junction All Around structure, where a deep trench structure surrounds and encloses a P-N junction or a MOS structure, is created and applied in various rectifiers. In one embodiment, multiple deep trenches in ring shape enclosed a vertical P-N junction. For each deep trench, a corresponding wider ring-shape P+ region is created on top of a N− epi layer. This enclosed deep trench surrounding a vertical P-N junction and a thinner N− epitaxial layer allow higher reverse bias voltage and low leakage current. In another embodiment, an enclosed deep trench in ring shape surrounds a horizontal P-N junction, which results in a planar N-channel MOS during forward bias. The structure can be extended to multiple deep trenches with associated horizontal P-N junctions. In a further embodiment, an enclosed deep trench in ring shape surrounds a vertical MOS structure plus a shallow trench gate in the center to create yet another device with very high breakdown voltage and very low leakage current. This structure can be extended to multiple deep trenches and shallow trenches as well.

公开(公告)号：US10468604B2

公开(公告)日：2019-11-05

申请号：US15393173

申请日：2016-12-28

Applicant: KOREA RESEARCH INSTITUTE OF STANDARDS AND SCIENCE

Inventor： Ansoon Kim ,  Songwoung Hong ,  Jeong Won Kim ,  Hyuksang Kwon

IPC: H01L21/02 ,  H01L51/00 ,  C01B25/02 ,  H01L29/70 ,  H01L29/66 ,  H01L29/861 ,  H01L29/24 ,  H01L51/42 ,  H01L51/05 ,  H01L29/778

Abstract: Provided are a lateral p-n junction black phosphorus thin film, and a method of manufacturing the same, and specifically, a lateral p-n junction black phosphorus thin film in which a p-type black phosphorus thin film having a p-type semiconductor property and a n-type black phosphorus thin film having a n-type semiconductor property form a lateral junction by modifying some regions on a surface of the black phosphorus thin film through light irradiation with a compound having a specific chemical structure, and a method of manufacturing the same.

公开(公告)号：US10205017B2

公开(公告)日：2019-02-12

申请号：US14037205

申请日：2013-09-25

Applicant: Madhur Bobde

Inventor： Madhur Bobde

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/70 ,  H01L29/732 ,  H01L21/8249 ,  H01L27/07

Abstract: A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer to form a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) that comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate. The drain region interfaces with the body region constituting a junction diode. The drain region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode. The body regions further comprises a surface body contact region electrically connected to a body-to-source short-connection thus connecting the body region to the bottom electrode functioning as the source/emitter terminal.

公开(公告)号：US10128227B2

公开(公告)日：2018-11-13

申请号：US15671816

申请日：2017-08-08

Applicant: Silergy Semiconductor Technology (Hangzhou) Ltd.

Inventor： Shijun Wang ,  Fei Yao ,  Dengping Yin

IPC: H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11 ,  H01L27/02 ,  H01L21/761 ,  H01L21/762 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/06 ,  H01L27/07

Abstract: Disclosed is a method for manufacturing an ESD protection device. The ESD protection device includes a rectifier diode and an open-base bipolar transistor, the anode of the rectifier diode is the first doped region and the cathode of the rectifier diode is the semiconductor substrate, the emitter region, base region and collector region of the open-base bipolar transistor are the second doped region, the epitaxial semiconductor layer and semiconductor substrate, respectively, the first doped region and the second doped region extend through the doped region into the epitaxial semiconductor layer by a predetermined depth. The doped region can suppress the induced doped region around the second doped region, so that the parasitic capacitance of the open-base bipolar transistor is reduced and the response speed is improved.

公开(公告)号：US20150255362A1

公开(公告)日：2015-09-10

申请号：US14200732

申请日：2014-03-07

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Christian Hecht ,  Roland Rupp ,  Andre Kabakow

IPC: H01L23/31 ,  H01L29/872 ,  H01L29/808 ,  H01L29/78 ,  H01L21/56 ,  H01L21/308 ,  H01L29/66 ,  H01L27/06 ,  H01L23/29 ,  H01L29/47 ,  H01L21/283 ,  H01L21/02 ,  H01L21/28 ,  H01L29/70

CPC classification number: H01L23/3171 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28247 ,  H01L21/283 ,  H01L21/3081 ,  H01L21/56 ,  H01L23/29 ,  H01L23/3192 ,  H01L27/0629 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/1066 ,  H01L29/4236 ,  H01L29/47 ,  H01L29/66674 ,  H01L29/66901 ,  H01L29/70 ,  H01L29/7397 ,  H01L29/7801 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/808 ,  H01L29/8083 ,  H01L29/8611 ,  H01L29/872 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10331 ,  H01L2924/10335 ,  H01L2924/10346 ,  H01L2924/10373 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor body having a first surface, a contact electrode on the first surface, and a passivation layer on the first surface adjacent the contact electrode and partially overlapping the contact electrode. The passivation layer comprises a layer stack with a first layer comprising an oxide on the first surface, and a second layer comprising a nitride on the first layer.

Abstract translation: 半导体器件包括具有第一表面的半导体本体，第一表面上的接触电极和与接触电极相邻的第一表面上的钝化层，并且部分地与接触电极重叠。 钝化层包括具有在第一表面上包含氧化物的第一层的层叠层，以及在第一层上包含氮化物的第二层。

公开(公告)号：US20150236140A1

公开(公告)日：2015-08-20

申请号：US14430585

申请日：2013-09-20

Applicant: PST SENSORS (PROPRIETARY) LIMITED

Inventor： David Thomas Britton ,  Margit Haerting ,  Stanley Douglas Walton

IPC: H01L29/70 ,  H01L29/06 ,  H01L29/04

CPC classification number: H01L29/705 ,  H01C7/1013 ,  H01L29/04 ,  H01L29/0692 ,  H01L29/72 ,  H01L49/02 ,  H01L51/0036 ,  H01L51/0037 ,  H01L51/0504

Abstract: An electronic device and a method of fabricating an electronic device are disclosed. The device includes a body of semiconductor material, and a conductive material defining at least three conducting contacts to form respective terminals. The semiconductor material and the conducting contacts overlap at least partially to define the device, so that the electrical characteristics of the device between any pair of terminals correspond to those of a varistor. The body of semiconductor material may be a layer deposited by printing or coating. The varistor characteristics between each pair of terminals enable switching of an electrical current between one terminal and any two other terminals in such a manner that when there is a positive current into a first terminal, there is a negligible current through a second terminal at which a positive potential is applied and a positive current out of a third terminal which is held at a negative potential with respect to the second terminal. When there is a negative current outwards of the first terminal, there is a positive current into the second terminal and a negligible current through the third terminal.

Abstract translation: 公开了电子设备和制造电子设备的方法。 该装置包括半导体材料体和限定至少三个导电触点以形成相应端子的导电材料。 半导体材料和导电触头至少部分地重叠以限定器件，使得任何一对端子之间的器件的电特性对应于压敏电阻器的电特性。 半导体材料的主体可以是通过印刷或涂布沉积的层。 每对端子之间的变阻器特性使得能够以一种方式切换一个端子和任何两个其它端子之间的电流，使得当存在进入第一端子的正电流时，通过第二端子存在可忽略的电流， 施加正电位，并且相对于第二端子保持在负电位的第三端子中的正电流。 当第一端子有向外的负电流时，在第二端子中存在正电流，并且通过第三端子具有可忽略的电流。

公开(公告)号：US09105486B2

公开(公告)日：2015-08-11

申请号：US14150477

申请日：2014-01-08

Applicant: MITSUBISHI ELECTRIC CORPORATION

Inventor： Atsushi Narazaki

IPC: H01L29/70 ,  H01L29/06 ,  H01L29/739 ,  H01L29/861

CPC classification number: H01L29/0615 ,  H01L29/0696 ,  H01L29/7393 ,  H01L29/7397 ,  H01L29/8611

Abstract: A semiconductor device includes a first conductive type semiconductor substrate, a second conductive type active region formed on a top surface side of the semiconductor substrate, a second conductive type inside VLD region formed to contact the active region on the top surface side in a plan view, and a second conductive type well region formed to contact a portion opposite to the portion contacting the active region of the inside VLD region on the top surface side in a plan view. The well region is formed to be deeper than the active region. The inside VLD region has the same depth as that of the active region in the portion contacting the active region, the depth gradually increasing from the active region toward the well region and becoming the same as the depth of the well region in the portion contacting the well region.

Abstract translation: 半导体器件包括第一导电型半导体衬底，形成在半导体衬底的顶表面侧上的第二导电型有源区，在俯视图中形成为与顶表面侧上的有源区接触的第二导电型内部VLD区 以及第二导电型阱区，形成为在平面图中与顶表面侧的与内部VLD区的有源区接触的部分相接触的部分。 阱区形成为比活性区更深。 内部VLD区域的深度与有源区域接触的部分的有源区域的深度相同，深度从有源区域朝向阱区域逐渐增加，并且与接触该区域的部分中的阱区域的深度相同 井区。