公开(公告)号：US11810779B2

公开(公告)日：2023-11-07

申请号：US17841781

申请日：2022-06-16

申请人： Infineon Technologies AG

发明人： Sophia Friedler ,  Bernhard Goller ,  Iris Moder ,  Ingo Muri

IPC分类号： H01L21/02 ,  H01L21/465 ,  H01L21/8258

CPC分类号： H01L21/0203 ,  H01L21/02019 ,  H01L21/465 ,  H01L21/8258

摘要： A method includes: in a semiconductor wafer having a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a front surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10−2 times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer, wherein forming the porous region comprises bringing in contact a porosifying agent with the front surface of the first semiconductor layer and applying a voltage between the first semiconductor layer and a first electrode that is in contact with the porosifying agent, wherein applying the voltage comprises applying the voltage between the first electrode and an edge region of the first semiconductor layer.

公开(公告)号：US20230327007A1

公开(公告)日：2023-10-12

申请号：US18333982

申请日：2023-06-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  National Yang Ming Chiao Tung University

发明人： Shu-Jui CHANG ,  Shin-Yuan WANG ,  Yu-Che HUANG ,  Chun-Liang LIN ,  Chao-Hsin CHIEN ,  Chenming HU

IPC分类号： H01L29/76 ,  H01L27/092 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/45 ,  H01L29/775 ,  H01L21/02 ,  H01L21/443 ,  H01L21/465 ,  H01L29/66

CPC分类号： H01L29/7606 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/775 ,  H01L21/02568 ,  H01L21/443 ,  H01L21/465 ,  H01L29/45

摘要： A method includes forming a 2-D material layer over a substrate, wherein the 2-D material layer comprises transition metal atoms and chalcogen atoms; forming a gate structure over the 2-D material layer; supplying chemical molecules to the 2-D material layer, such that atoms of the chemical molecules react with portions of the chalcogen atoms to weaken covalent bonds between the portions of the chalcogen atoms and the transition metal atoms; and forming source/drain contacts over the 2-D material layer, wherein contact metal atoms of the source/drain contacts form metallic bonds with the transition metal atoms of the 2-D material layer.

公开(公告)号：US11764307B2

公开(公告)日：2023-09-19

申请号：US17749106

申请日：2022-05-19

申请人： LG Display Co., Ltd.

发明人： Seung-Jin Kim ,  Jee-Ho Park ,  Seo-Yeon Im

IPC分类号： G09G3/32 ,  H01L29/786 ,  H01L29/24 ,  H01L27/12 ,  H01L29/66 ,  G09G3/3225 ,  G09G3/3266 ,  H01L29/423 ,  H01L21/465 ,  H10K59/12

CPC分类号： H01L29/78693 ,  G09G3/3225 ,  G09G3/3266 ,  H01L27/1225 ,  H01L29/247 ,  H01L29/66969 ,  H01L29/78696 ,  G09G2300/0809 ,  H01L21/465 ,  H01L29/42384 ,  H01L29/78633 ,  H10K59/12

摘要： Disclosed are a thin film transistor having an oxide semiconductor layer which is applicable to a flat display device requiring high-speed driving due to ultra-high definition, a gate driver including the same, and a display device including the same. The thin film transistor includes a first oxide semiconductor layer formed of iron-indium-zinc oxide (FIZO) and a second oxide semiconductor layer formed of indium-gallium-zinc oxide (IGZO), thus being capable of exhibiting effects, such as high reliability and high electron mobility.

公开(公告)号：US20230250534A1

公开(公告)日：2023-08-10

申请号：US18192983

申请日：2023-03-30

申请人： ASM IP HOLDING B.V.

发明人： Jani Hämäläinen ,  Mikko Ritala ,  Markku Leskelä

IPC分类号： C23C16/56 ,  H01L21/02 ,  C23C16/30 ,  C23C16/455 ,  C23F1/12 ,  H01L21/465

CPC分类号： C23C16/56 ,  H01L21/02568 ,  H01L21/0262 ,  C23C16/305 ,  C23C16/45534 ,  C23F1/12 ,  H01L21/465

摘要： Vapor deposition methods for depositing transition metal dichalcogenide (TMDC) films, such as rhenium sulfide thin films, are provided. In some embodiments TMDC thin films are deposited using a deposition cycle in which a substrate in a reaction space is alternately and sequentially contacted with a vapor phase transition metal precursor, such as a transition metal halide, a reactant comprising a reducing agent, such as NH3 and a chalcogenide precursor. In some embodiments rhenium sulfide thin films are deposited using a vapor phase rhenium halide precursor, a reducing agent and a sulfur precursor. The deposited TMDC films can be etched by chemical vapor etching using an oxidant such as O2 as the etching reactant and an inert gas such as N2 to remove excess etching reactant. The TMDC thin films may find use, for example, as 2D materials.

公开(公告)号：US11695078B2

公开(公告)日：2023-07-04

申请号：US17114765

申请日：2020-12-08

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Junichi Koezuka ,  Masami Jintyou ,  Yukinori Shima

IPC分类号： H01L29/786 ,  H01L29/49 ,  H01L29/417 ,  H01L29/24 ,  H01L29/04 ,  H01L27/12 ,  H01L29/66 ,  H01L21/02 ,  H01L21/477 ,  H01L21/465 ,  H01L21/4757 ,  H01L29/423 ,  H10K59/12 ,  H10K59/121

CPC分类号： H01L29/7869 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/0262 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/465 ,  H01L21/477 ,  H01L21/47573 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/045 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78696 ,  H10K59/1201 ,  H10K59/1213

摘要： The reliability of a transistor including an oxide semiconductor can be improved by suppressing a change in electrical characteristics. A transistor included in a semiconductor device includes a first oxide semiconductor film over a first insulating film, a gate insulating film over the first oxide semiconductor film, a second oxide semiconductor film over the gate insulating film, and a second insulating film over the first oxide semiconductor film and the second oxide semiconductor film. The first oxide semiconductor film includes a channel region in contact with the gate insulating film, a source region in contact with the second insulating film, and a drain region in contact with the second insulating film. The second oxide semiconductor film has a higher carrier density than the first oxide semiconductor film.

公开(公告)号：US11670688B2

公开(公告)日：2023-06-06

申请号：US16764615

申请日：2018-11-15

申请人： FLOSFIA INC.

发明人： Tokiyoshi Matsuda ,  Masahiro Sugimoto ,  Takashi Shinohe

IPC分类号： H01L29/24 ,  C23C16/448 ,  H01L21/02 ,  H01L21/443 ,  H01L21/465 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H02M3/335

CPC分类号： H01L29/24 ,  C23C16/4481 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/443 ,  H01L21/465 ,  H01L29/66969 ,  H01L29/7397 ,  H01L29/7806 ,  H01L29/7813 ,  H02M3/33576

摘要： The disclosure provides a semiconductor apparatus capable of keeping a semiconductor characteristics and realizing excellent semiconductor properties even when using an n type semiconductor (gallium oxide, for example) having a low loss at a high voltage and having much higher dielectric breakdown electric field strength than SiC. A semiconductor apparatus includes a gate electrode and a channel layer formed of a channel directly or through other layers on a side wall of the gate electrode, and wherein a portion of or whole the channel layer may be a p type oxide semiconductor (iridium oxide, for example).

公开(公告)号：US20230120305A1

公开(公告)日：2023-04-20

申请号：US17965888

申请日：2022-10-14

申请人： ADVANCED MICRO DEVICES, INC.

发明人： CHIA-HAO CHENG ,  RAHUL AGARWAL ,  CHINTAN BUCH ,  ARSALAN ALAM

IPC分类号： H01L21/66 ,  H01L23/48 ,  H01L23/00 ,  H01L21/463 ,  H01L21/465 ,  H01L21/3205

摘要： A method includes applying a temporary pad to a conductive pad of a semiconductor die. After testing the semiconductor die, the temporary pad is removed from the conductive pad.

公开(公告)号：US20230115949A1

公开(公告)日：2023-04-13

申请号：US17646487

申请日：2021-12-30

申请人： HON HAI PRECISION INDUSTRY CO., LTD.

发明人： Kuang-Hao CHIANG

IPC分类号： H01L21/465 ,  H01L25/065 ,  H01L21/3213

摘要： A manufacturing method of a semiconductor structure includes the following operations. A stacked structure is formed on a substrate. The stacked structure includes semiconductor layers and sacrificial layers that are alternately stacked, in which the sacrificial layers include germanium, and germanium concentrations of the sacrificial layers decrease from bottom to top. A dummy gate structure is formed on the stacked structure. A spacer is formed on both sides of the dummy gate structure. The dummy gate structure is removed, thereby forming an opening. The sacrificial layers are removed from the opening. A gate structure is formed to cover the semiconductor layers. In another manufacturing method, the stacked structure includes semiconductor layers and sacrificial layers that are alternately stacked, in which thicknesses of the semiconductor layers increase from bottom to top, or thicknesses of the sacrificial layers increase from bottom to top.

公开(公告)号：US20230081110A1

公开(公告)日：2023-03-16

申请号：US17890795

申请日：2022-08-18

申请人： DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation

发明人： KATSUHIRO KUTSUKI ,  KEITA KATAOKA ,  DAIGO KIKUTA ,  HIROKI MIYAKE ,  SHUHEI ICHIKAWA ,  YOSHITAKA NAGASATO

IPC分类号： H01L29/872 ,  H01L29/24 ,  H01L21/465

摘要： In a surface treatment method for a gallium oxide-based semiconductor substrate, a surface of the gallium oxide-based semiconductor substrate is flattened by dry etching with a self-bias of 150 V or more. After the surface of the gallium oxide-based semiconductor substrate is flattened, the surface of the gallium oxide-based semiconductor substrate is washed with a chemical solution containing H2SO4 to expose a step terrace structure on the surface of the gallium oxide-based semiconductor substrate.

公开(公告)号：US20230018338A1

公开(公告)日：2023-01-19

申请号：US17807794

申请日：2022-06-20

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Kejun MU

IPC分类号： H01L21/762 ,  H01L21/465

摘要： A method for manufacturing a semiconductor structure includes the following operations. A base and a dielectric layer arranged on the base are provided. A first conductive pillar, a second conductive pillar and a third conductive pillar arranged in the dielectric layer are formed. A mask layer is formed. A portion of a thickness of the third conductive pillar is etched by using the third mask layer as a mask to form a third lower conductive pillar and a third upper conductive pillar stacked on one another, in which the third upper conductive pillar, the third lower conductive pillar and the dielectric layer are configured to form at least one groove. A cover layer filling the at least one groove is formed, in which the cover layer exposes the top surface of the third upper conductive pillar.