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1.
公开(公告)号:US12132648B2
公开(公告)日:2024-10-29
申请号:US17594543
申请日:2020-03-23
发明人: David Charles Hewson , Partha Kundu
IPC分类号: H04L45/28 , G06F9/50 , G06F9/54 , G06F12/0862 , G06F12/1036 , G06F12/1045 , G06F13/14 , G06F13/16 , G06F13/28 , G06F13/38 , G06F13/40 , G06F13/42 , G06F15/173 , H04L1/00 , H04L43/0876 , H04L43/10 , H04L45/00 , H04L45/02 , H04L45/021 , H04L45/028 , H04L45/12 , H04L45/122 , H04L45/125 , H04L45/16 , H04L45/24 , H04L45/42 , H04L45/745 , H04L45/7453 , H04L47/10 , H04L47/11 , H04L47/12 , H04L47/122 , H04L47/20 , H04L47/22 , H04L47/24 , H04L47/2441 , H04L47/2466 , H04L47/2483 , H04L47/30 , H04L47/32 , H04L47/34 , H04L47/52 , H04L47/62 , H04L47/625 , H04L47/6275 , H04L47/629 , H04L47/76 , H04L47/762 , H04L47/78 , H04L47/80 , H04L49/00 , H04L49/101 , H04L49/15 , H04L49/90 , H04L49/9005 , H04L49/9047 , H04L67/1097 , H04L69/22 , H04L69/40 , H04L69/28
CPC分类号: H04L45/28 , G06F9/505 , G06F9/546 , G06F12/0862 , G06F12/1036 , G06F12/1063 , G06F13/14 , G06F13/16 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F13/28 , G06F13/385 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F15/17331 , H04L1/0083 , H04L43/0876 , H04L43/10 , H04L45/02 , H04L45/021 , H04L45/028 , H04L45/122 , H04L45/123 , H04L45/125 , H04L45/16 , H04L45/20 , H04L45/22 , H04L45/24 , H04L45/38 , H04L45/42 , H04L45/46 , H04L45/566 , H04L45/70 , H04L45/745 , H04L45/7453 , H04L47/11 , H04L47/12 , H04L47/122 , H04L47/18 , H04L47/20 , H04L47/22 , H04L47/24 , H04L47/2441 , H04L47/2466 , H04L47/2483 , H04L47/30 , H04L47/32 , H04L47/323 , H04L47/34 , H04L47/39 , H04L47/52 , H04L47/621 , H04L47/6235 , H04L47/626 , H04L47/6275 , H04L47/629 , H04L47/76 , H04L47/762 , H04L47/781 , H04L47/80 , H04L49/101 , H04L49/15 , H04L49/30 , H04L49/3009 , H04L49/3018 , H04L49/3027 , H04L49/90 , H04L49/9005 , H04L49/9021 , H04L49/9036 , H04L49/9047 , H04L67/1097 , H04L69/22 , H04L69/40 , G06F2212/50 , G06F2213/0026 , G06F2213/3808 , H04L69/28
摘要: A network interface controller (NIC) capable of efficient load balancing among the hardware engines is provided. The NIC can be equipped with a plurality of ordering control units (OCUs), a queue, a selection logic block, and an allocation logic block. The selection logic block can determine, from the plurality of OCUs, an OCU for a command from the queue, which can store one or more commands. The allocation logic block can then determine a selection setting for the OCU, select an egress queue for the command based on the selection setting, and send the command to the egress queue.
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公开(公告)号:US12130932B2
公开(公告)日:2024-10-29
申请号:US17381456
申请日:2021-07-21
申请人: Dell Products, L.P.
发明人: Chandrasekhar Mugunda , Rama Rao Bisa , Viswanath Ponnuru , Dharma Bhushan Ramaiah , Shinose Abdul Rahiman , Vineeth Radhakrishnan , Chitrak Gupta
IPC分类号: G06F21/60 , G06F9/4401 , G06F13/40 , G06F13/42 , G06F21/85
CPC分类号: G06F21/606 , G06F9/4401 , G06F13/4031 , G06F13/405 , G06F13/4282 , G06F21/85 , G06F2213/0016 , G06F2221/2125
摘要: According to one embodiment, a path obfuscation system includes first and second hardware devices, and first and second interfaces configured to provide communication between the first and second hardware devices using a security protocol and data model (SPDM) protocol. The first hardware device comprises computer-executable instructions to receive a message to be transmitted to the second hardware device, segment the message into multiple groups of packets, and randomly select either the first or second interface to transmit each group of packet to the second hardware device.
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公开(公告)号:US12130764B2
公开(公告)日:2024-10-29
申请号:US18317095
申请日:2023-05-15
发明人: Jingsheng Chen , Mingliang Sun , Honghai Li , Liping He , Wenqing Xiao , Longhua Dai
CPC分类号: G06F13/4022 , G06F1/266 , G06F3/14 , G06F13/4282 , G06F2213/0042
摘要: The present disclosure provides a control circuit of a blind-mating display having two Type-C interfaces, a control device thereof, and a control method thereof. The control circuit of the blind-mating display having two Type-C interfaces includes a display control module, a first Type-C interface module, a second Type-C interface module, a first switching switch module, a second switching switch module, and a dielectric module. The dielectric module is electrically connected to the first Type-C interface module, the second Type-C interface module, and the display control module. The first switching switch module is electrically connected to the first Type-C interface module, the second Type-C interface module, and the display control module. The second switching switch module is electrically connected to the first Type-C interface module, the second Type-C interface module, and the display control module. The present disclosure is alternately communicated with the source device and the PD device.
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公开(公告)号:US12130762B2
公开(公告)日:2024-10-29
申请号:US17836829
申请日:2022-06-09
发明人: Junyoung Moon , Sangmin Lee
CPC分类号: G06F13/385 , G06F13/4068 , G06F13/4282 , G06F21/44 , G06F2213/0042
摘要: A host system includes a connector having a structure connected to the device irrespective of a direction. The connector includes a plurality of pins disposed thereon. A connection direction detector is configured to detect a direction in which the device is connected to the host system by detecting a signal from at least one first pin of the plurality of pins. A setting controller is configured to receive, from the device, setting information related to a configuration supported by the device and control a configuration operation on the device based on direction information from the connection direction detection. The host system is configured to perform control such that a function module having a unique function included in the device is selectively enabled based on the setting information and the direction information.
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5.
公开(公告)号:US20240354183A1
公开(公告)日:2024-10-24
申请号:US18757861
申请日:2024-06-28
申请人: Pure Storage, Inc.
IPC分类号: G06F11/07 , G06F3/06 , G06F11/10 , G06F11/14 , G06F11/20 , G06F11/30 , G06F11/32 , G06F13/40 , G06F13/42 , G06F30/20 , G06N3/04 , G06N3/084 , G06N3/10 , G06Q10/0631 , G06Q10/20 , H03M13/00 , H03M13/15 , H03M13/29 , H03M13/37 , H04L9/08 , H04L9/14 , H04L9/32 , H04L9/40
CPC分类号: G06F11/0781 , G06F3/0604 , G06F3/0605 , G06F3/0619 , G06F3/0623 , G06F3/0629 , G06F3/064 , G06F3/0644 , G06F3/0653 , G06F3/0659 , G06F11/0709 , G06F11/0727 , G06F11/0751 , G06F11/079 , G06F11/0793 , G06F11/1076 , G06F11/1451 , G06F11/2094 , G06F11/3034 , G06F11/3051 , G06F11/3055 , G06F11/327 , G06F13/4022 , G06F13/4282 , G06F30/20 , G06N3/04 , G06N3/084 , G06N3/10 , G06Q10/063116 , G06Q10/06316 , G06Q10/20 , H03M13/1515 , H03M13/2909 , H03M13/3761 , H03M13/616 , H04L9/0869 , H04L9/0894 , H04L9/14 , H04L9/3242 , H04L63/0428 , H04L63/061 , H04L63/101 , G06F3/067 , G06F2201/84
摘要: A method for execution by a storage network processor starts by monitoring a plurality of storage network storage nodes to determine whether a storage node requires maintenance. The method continues by determining one or more maintenance tasks for the storage node and updating a status of the storage node to indicate that the storage node is in a maintenance mode. The method then continues by facilitating execution of the one or more maintenance tasks, capturing any resulting maintenance task results and determining whether a maintenance task of the one or more maintenance tasks has generated an exception. Finally, in response to a determination that a maintenance task has generated an exception, the method continues by transmitting a message indicating the exception to a storage network entity.
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公开(公告)号:US12124394B2
公开(公告)日:2024-10-22
申请号:US17804451
申请日:2022-05-27
发明人: Darin Lee Frink , Peter George Ross
IPC分类号: H05K7/20 , G06F1/18 , G06F1/20 , G06F1/3287 , G06F3/06 , G06F13/40 , G11B33/12 , G11B33/14 , H05K7/14
CPC分类号: G06F13/4068 , G06F1/181 , G06F1/187 , G06F1/20 , G06F1/206 , G06F1/3287 , G06F3/0619 , G06F3/0655 , G06F3/0689 , G11B33/128 , G11B33/142 , H05K7/1457 , H05K7/20572
摘要: A system for storing data includes a rack, one or more data storage modules coupled to the rack, and one or more data control modules coupled to the rack. The data storage modules may include a chassis, two or more backplanes coupled to the chassis, and one or more mass storage devices (for example, hard disk drives) coupled to the backplanes. The data control modules may access the mass storage devices in the data storage modules.
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公开(公告)号:US12124393B2
公开(公告)日:2024-10-22
申请号:US17587695
申请日:2022-01-28
CPC分类号: G06F13/4068 , G06F13/4282 , G06F2213/0016
摘要: An example system includes: a device coupled to a data line, the device configured to: send a first command on the data line, the first command including a first address; after sending the first command, read a first value on the data line, the first value including data from a first target device and a second target device; responsive to reading the first value, send a second command including the first address and data representing the first value on the data line; send a third command on the data line, the third command including the first address; after sending the third command, read a second value on the data line, the second value including data from the first target device and the second target device; responsive to reading the second value, send a fourth command on the data line, the fourth command including the first address.
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公开(公告)号:US20240345981A1
公开(公告)日:2024-10-17
申请号:US18624296
申请日:2024-04-02
发明人: Tal E. Volk , Farshid Tabrizi
CPC分类号: G06F13/4081 , G06F13/124 , G06F2213/3854
摘要: A dual connection peripheral device has a housing. A captive input/output cable is disposed at least partially within the housing and selectively connects the dual connection peripheral device to a host device. An auxiliary input/output port is disposed on the housing and selectively connects to the host. A control circuit is operatively coupled to the captive input/output cable and auxiliary input/output port and selectively connects one of the captive input/output cable and the auxiliary input/output port to the host device.
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公开(公告)号:US12118451B2
公开(公告)日:2024-10-15
申请号:US15423272
申请日:2017-02-02
发明人: Giuseppe Desoli , Thomas Boesch , Nitin Chawla , Surinder Pal Singh , Elio Guidetti , Fabio Giuseppe De Ambroggi , Tommaso Majo , Paolo Sergio Zambotti
IPC分类号: G06N3/04 , G06F30/327 , G06F30/34 , G06F30/347 , G06N3/044 , G06N3/045 , G06N3/0464 , G06N3/047 , G06N3/084 , G06N20/00 , G06N20/10 , G06F9/445 , G06F13/40 , G06F15/78 , G06F115/02 , G06F115/08 , G06N3/063 , G06N3/08 , G06N7/01
CPC分类号: G06N3/0464 , G06F30/327 , G06F30/34 , G06F30/347 , G06N3/044 , G06N3/045 , G06N3/047 , G06N3/084 , G06N20/00 , G06N20/10 , G06F9/44505 , G06F13/4022 , G06F15/7817 , G06F2115/02 , G06F2115/08 , G06N3/04 , G06N3/063 , G06N3/08 , G06N7/01
摘要: Embodiments are directed towards a system on chip (SoC) that implements a deep convolutional network heterogeneous architecture. The SoC includes a system bus, a plurality of addressable memory arrays coupled to the system bus, at least one applications processor core coupled to the system bus, and a configurable accelerator framework coupled to the system bus. The configurable accelerator framework is an image and deep convolutional neural network (DCNN) co-processing system. The SoC also includes a plurality of digital signal processors (DSPs) coupled to the system bus, wherein the plurality of DSPs coordinate functionality with the configurable accelerator framework to execute the DCNN.
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10.
公开(公告)号:US12117955B2
公开(公告)日:2024-10-15
申请号:US17951473
申请日:2022-09-23
CPC分类号: G06F13/423 , G06F13/405
摘要: This application provides a spread spectrum clock negotiation method, and a peripheral component interconnect express device and system, to implement dynamic negotiation between a transmit end and a receive end on an SSC capability in the peripheral component interconnect express system. The method includes: A second PCIe device generates first indication information, where the first indication information is used to indicate whether the second PCIe device has a spread spectrum clock capability. The second PCIe device sends the first indication information to a first PCIe device. The first PCIe device determines, based on the first indication information, whether to perform spread spectrum clock on a reference clock of the first PCIe device.
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