公开(公告)号：US20040157418A1

公开(公告)日：2004-08-12

申请号：US10722867

申请日：2003-11-26

申请人： International Business Machines Corporation

发明人： Matthew J. Breitwisch ,  Chung H. Lam ,  James A. Slinkman

IPC分类号： H01L021/425

CPC分类号： H01L21/823878 ,  H01L21/823892

摘要： A method of forming retrograde n-wells and p-wells. A first mask is formed on the substrate and the n-well implants are carried out. Then the mask is thinned, and a deep p implant is carried out with the thinned n-well mask in place. This prevents Vt shifts in FETs formed in the n-well adjacent the nwell-pwell interface. The thinned mask is then removed, a p-well mask is put in place, and the remainder of the p-well implants are carried out.

摘要翻译： 形成逆行n井和p井的方法。 在基板上形成第一掩模，并执行n阱注入。 然后将掩模变薄，并用较薄的n面罩进行深度p植入。 这防止了在n阱中形成的在n阱中形成的FET的Vt偏移。 然后去除变薄的掩模，将p-阱掩模放置就位，并且执行其余的p阱注入。

公开(公告)号：US20040147082A1

公开(公告)日：2004-07-29

申请号：US10747830

申请日：2003-12-29

发明人： Dae Kyeun Kim

IPC分类号： H01L021/336 ,  H01L021/425 ,  H01L021/4763

CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76834 ,  H01L29/665

摘要： A method of manufacturing a semiconductor device with a transistor comprising an LDD region and a silicide layer is disclosed. The method may include forming a gate electrode on a substrate, forming a first preliminary source/drain region with shallow junction through an ion implantation process using the gate electrode as a mask, and forming a ILD pattern with contact holes on the substrate including the gate electrode, the contact holes exposing the top of the gate electrode and some part of the first preliminary source/drain region. The method may also include forming an expanded source/drain region through an ion implantation process using the ILD pattern as a mask, forming a silicide layer on the top of the gate electrode and the expanded source/drain region, and forming contact plugs by filling the contact holes with metal.

摘要翻译： 公开了一种制造具有包括LDD区和硅化物层的晶体管的半导体器件的方法。 该方法可以包括在衬底上形成栅电极，通过使用栅电极作为掩模的离子注入工艺形成具有浅结的第一初级源极/漏极区域，以及在包括栅极的衬底上形成具有接触孔的ILD图案 电极，接触孔暴露出栅极电极的顶部和第一初级源极/漏极区域的一部分。 该方法还可以包括通过使用ILD图案作为掩模的离子注入工艺形成扩展的源极/漏极区域，在栅电极的顶部和扩展的源极/漏极区域上形成硅化物层，以及通过填充形成接触塞 接触孔用金属。

公开(公告)号：US20040126999A1

公开(公告)日：2004-07-01

申请号：US10668682

申请日：2003-09-22

申请人： APPLIED MATERIALS, INC.

发明人： Balasubramanian Ramachandran ,  Ravi Jallepally ,  Ryan C. Boas ,  Sundar Ramamurthy ,  Amir Al-Bayati ,  Houda Graoui ,  Joseph M. Spear

IPC分类号： H01L021/04 ,  H01L021/425

CPC分类号： H01L21/324 ,  H01L21/26513 ,  H01L21/2686 ,  H01L21/67109 ,  H01L21/67115

摘要： Lamp based spike annealing was improved to address the aggressive requirements of

摘要翻译： 改进了基于灯的尖峰退火以满足<100nm超浅结点（USJ）技术的积极要求。 改进的重点是提高冷却速率，从而提高尖峰锐度。 然后将具有不同离子注入能量和剂量的硼离子注入衬底退火以表征尖峰退火的改进。 在具有改进的尖峰轮廓退火的基底上实现了薄膜电阻和结深度的大于10％的改善。 改进的尖峰退火具有与标准尖峰退火相同的可比均匀性。

公开(公告)号：US20040121567A1

公开(公告)日：2004-06-24

申请号：US10655041

申请日：2003-09-05

申请人： Nat'l Inst. of Advan. Industrial Science and Tech. ,  NEC Corporation

发明人： Toshihiko Kanayama ,  Takehide Miyazaki ,  Hidefumi Hiura

IPC分类号： H01L021/04 ,  H01L021/425

CPC分类号： H01L29/6659 ,  H01L21/2257

摘要： A doping method includes the step of attaching molecules or clusters to the surface of a semiconductor substrate to enable charge transfer from the molecules or clusters to the substrate surface, thereby inducing carriers underneath the substrate surface. A semiconductor device is fabricated through attachment of molecules or clusters to the surface of a semiconductor substrate. The attachment enables charge transfer from the molecules or clusters to the substrate surface to induce carriers underneath the substrate surface.

摘要翻译： 掺杂方法包括将分子或簇附着到半导体衬底的表面以使电荷从分子或簇转移到衬底表面的步骤，从而在衬底表面下诱导载流子。 通过将分子或簇附着到半导体衬底的表面来制造半导体器件。 该附件使得能够从分子或簇到基底表面的电荷转移以在基底表面下诱导载体。

公开(公告)号：US20040102039A1

公开(公告)日：2004-05-27

申请号：US10636854

申请日：2003-08-06

发明人： Kwan-Yong Lim ,  Heung-Jae Cho

IPC分类号： H01L021/4763 ,  H01L021/425 ,  H01L021/44

CPC分类号： H01L21/76877 ,  H01L21/76895 ,  H01L21/823475

摘要： The present invention relates to a method for forming a landing plug capable of securing a low resistance by employing a selective epitaxial growth technique to meet demands of high-integration and high-speed in a semiconductor device. The method includes the steps of: forming an inter-layer insulation layer on a substrate; forming a contact hole by etching the inter-layer insulation layer until exposing a partial portion of the substrate; forming a first conductive layer with a predetermined thickness inside of the contact hole, the first conductive layer being made of a silicon layer; forming a second conductive layer on the inter-layer insulation layer in such a manner of being buried into the contact hole in which the silicon layer is formed; and performing a blanket etch process to the second conductive layer until exposing surfaces of the inter-layer insulation layer and the hard mask so that a landing plug is formed.

摘要翻译： 本发明涉及一种用于形成能够通过选择性外延生长技术来确保低电阻的层叠塞的方法，以满足半导体装置中高集成度和高​​速度的要求。 该方法包括以下步骤：在衬底上形成层间绝缘层; 通过蚀刻所述层间绝缘层直到暴露所述衬底的部分部分来形成接触孔; 在所述接触孔内形成具有预定厚度的第一导电层，所述第一导电层由硅层制成; 在层间绝缘层上形成第二导电层，以埋入形成硅层的接触孔中; 以及对所述第二导电层进行覆盖蚀刻处理，直到所述层间绝缘层和所述硬掩模的表面露出，从而形成着陆塞。

公开(公告)号：US20040102026A1

公开(公告)日：2004-05-27

申请号：US10305724

申请日：2002-11-26

发明人： Nga-Ching Wong ,  Timothy Thurgate ,  Sameer S. Haddad

IPC分类号： H01L031/119 ,  H01L031/113 ,  H01L029/76 ,  H01L029/94 ,  H01L021/425

CPC分类号： H01L27/11521 ,  H01L21/26586 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/1045 ,  H01L29/66825 ,  H01L29/66833

摘要： A lateral doped channel. A first doping material is implanted substantially vertically into a region adjacent to a gate structure. A diffusion process diffuses the first doping material into a channel region beneath the gate structure. A second doping material is implanted substantially vertically into the region adjacent to a gate structure. The second implantation forms source/drain regions and may terminate the channel region. The channel region thus comprises a laterally non-uniform doping profile which beneficially mitigates the short channel effect and is highly advantageous as compensation for manufacturing process variations in channel length.

摘要翻译： 横向掺杂通道。 第一掺杂材料基本上垂直地植入到与栅极结构相邻的区域中。 扩散过程将第一掺杂材料扩散到栅极结构下方的沟道区域中。 基本垂直地将第二掺杂材料注入到与栅极结构相邻的区域中。 第二注入形成源极/漏极区域并且可以终止沟道区域。 因此，通道区域包括横向不均匀的掺杂分布，其有利地减轻了短沟道效应，并且作为对通道长度的制造工艺变化的补偿是非常有利的。

公开(公告)号：US20040101999A1

公开(公告)日：2004-05-27

申请号：US10442226

申请日：2003-05-21

申请人： Renesas Technology Corp.

发明人： Hidekazu Oda ,  Hirokazu Sayama ,  Kazunobu Ohta ,  Kouhei Sugihara

IPC分类号： H01L021/00 ,  H01L021/336 ,  H01L021/8234 ,  H01L021/425

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/6659

摘要： A method of manufacturing a semiconductor device is provided which can suppress leakage current increases by making into silicide. Impurity that suppresses silicide formation reaction (suppression impurity), such as germanium, is introduced into source/drain regions (16, 36) from their upper surfaces. In the source/drain regions (16, 36), a region shallower than a region where the suppression impurity is distributed (50) is made into silicide, so that a silicide film (51) is formed in the source/drain regions (16, 36). Thus, by making the region shallower than the region (50) into silicide, it is possible to suppress that silicide formation reaction extends to the underside of the region to be made into silicide. This enables to reduce the junction leakage between the source/drain regions (16, 36) and a well region.

摘要翻译： 提供一种制造半导体器件的方法，其可以通过制造硅化物来抑制泄漏电流的增加。 抑制硅化物形成反应（抑制杂质）如锗的杂质从其上表面引入源/漏区（16,36）。 在源极/漏极区域（16,36）中，将比抑制杂质分布区域浅的区域（50）制成硅化物，使得在源极/漏极区域（16）中形成硅化物膜（51） ，36）。 因此，通过使区域（50）的区域比硅化物更浅，可以抑制硅化物形成反应延伸到要制成硅化物的区域的下侧。 这使得能够减少源极/漏极区域（16,36）与阱区域之间的结漏电。

公开(公告)号：US20040053482A1

公开(公告)日：2004-03-18

申请号：US10350184

申请日：2003-01-24

申请人： MITSUBISHI DENKI KABUSHIKI KAISHA

发明人： Eiji Hasunuma ,  Akira Matsumura

IPC分类号： H01L021/8242 ,  H01L021/425

CPC分类号： H01L27/10888 ,  H01L21/26586 ,  H01L21/76816 ,  H01L27/10855 ,  Y10S438/914 ,  Y10S438/944

摘要： When an opening diameter of a top end of a substantially column-shaped contact hole is S1, an opening diameter of a top end of a substantially column-shaped contact hole is T1, and a thickness of a silicon insulating layer is h, then contact holes are formed so as to satisfy the following conditional expression 1. T1/h

摘要翻译： 当基本为柱状的接触孔的顶端的开口直径为S1时，基本上为柱状的接触孔的顶端的开口直径为T1，硅绝缘层的厚度为h，然后接触 形成满足以下条件表达式1的孔。T1 / h

公开(公告)号：US20040014302A1

公开(公告)日：2004-01-22

申请号：US10199123

申请日：2002-07-22

发明人： Peter G. Tolchinsky ,  Irwin Yablok ,  Mohamad A. Shaheen

IPC分类号： H01L021/425

CPC分类号： H01L21/76254 ,  H01L21/76243 ,  H01L21/76256 ,  H01L21/76262

摘要： A method is provided for fabricating an SOI water. This may involve forming a silicon substrate and implanting oxygen into the substrate. Damaged portions of the implanted silicon may be healed/cured by CMP or anneal, for example. An epi layer may then be deposited over the healed/cured regions of the substrate. The substrate may then be annealed to form an insulative layer. The wafer may be thinned to provide the proper thickness of the epi layer.

摘要翻译： 提供了制造SOI水的方法。 这可能涉及形成硅衬底并将氧注入到衬底中。 植入的硅的损伤部分可以例如通过CMP来愈合/固化或退火。 然后可以将epi层沉积在衬底的愈合/固化区域上。 然后可以将衬底退火以形成绝缘层。 可以使晶片变薄以提供外延层的适当厚度。

公开(公告)号：US20040002202A1

公开(公告)日：2004-01-01

申请号：US10251491

申请日：2002-09-20

发明人： Thomas Neil Horsky ,  Dale Conrad Jacobson ,  Wade Allen Krull

IPC分类号： H01L021/8238 ,  H01L021/425

CPC分类号： H01L21/26513 ,  H01J2237/31701 ,  H01L21/26566 ,  H01L21/2658 ,  H01L21/425 ,  H01L21/823814 ,  H01L21/823842

摘要： A method of manufacturing a semiconductor device is described, wherein clusters of N- and P-type dopants are implanted to form the transistor structures in CMOS devices. For example, As4Hxnull clusters and either B10Hxnull or B10Hxnull clusters are used as sources of As and B doping, respectively, during the implants. An ion implantation system is described for the implantation of cluster ions into semiconductor substrates for semiconductor device manufacturing. A method of producing higher-order cluster ions of As, P, and B is presented, and a novel electron-impact ion source is described which favors the formation of cluster ions of both positive and negative charge states. The use of cluster ion implantation, and even more so the implantation of negative cluster ions, can significantly reduce or eliminate wafer charging, thus increasing device yields. A method of manufacturing a semiconductor device is further described, comprising the steps of: providing a supply of dopant atoms or molecules into an ionization chamber, combining the dopant atoms or molecules into clusters containing a plurality of dopant atoms, ionizing the dopant clusters into dopant cluster ions, extracting and accelerating the dopant cluster ions with an electric field, selecting the desired cluster ion by mass analysis, modifying the final implant energy of the cluster ion through post-analysis ion optics, and implanting the dopant cluster ions into a semiconductor substrate. In general, dopant clusters contain n dopant atoms where n can be 2, 3, 4 or any integer number. This method provides the advantages of increasing the dopant dose rate to n times the implantation current with an equivalent per dopant atom energy of 1/n times the cluster implantation energy. This is an effective method for making shallow transistor junctions, where it is desired to implant with a low energy per dopant atom.