公开(公告)号：US20040180522A1

公开(公告)日：2004-09-16

申请号：US10623563

申请日：2003-07-22

申请人： Renesas Technology Corp.

发明人： Yukio Nishida ,  Kazunobu Ohta

IPC分类号： H01L021/4763

CPC分类号： H01L21/82385 ,  H01L21/28114 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42376

摘要： A gate insulating film 4, two polysilicon films 5 and 7, and a silicon nitride film 9 are successively laminated on a semiconductor substrate 1 in this order. Each of the polysilicon films 5 and 7 contains phosphorus. The polysilicon film 5 has a region having a phosphorus concentration higher than that of the polysilicon film 7. Gate electrodes 10n, 10p, 40n, and 40p are formed on the gate insulating film 4 by partly etching the polysilicon films 5 and 7 and the silicon nitride film 9. In this case, the etching rate of the region of the polysilicon film 5, having a phosphorus concentration higher than that of the polysilicon film 7, is higher than that of the polysilicon film 7. Due to this difference, notches are formed at the bottom portions on side surfaces of respective gate electrodes 10p, 40n, and 40p.

摘要翻译： 依次将栅极绝缘膜4，两个多晶硅膜5和7以及氮化硅膜9依次层叠在半导体基板1上。 多晶硅膜5和7中的每一个都含有磷。 多晶硅膜5具有比多晶硅膜7的磷浓度高的区域。通过部分蚀刻多晶硅膜5和7，在栅极绝缘膜4上形成栅电极10n，10p，40n和40p，并且硅 在这种情况下，具有比多晶硅膜7高的磷浓度的多晶硅膜5的区域的蚀刻速率高于多晶硅膜7的蚀刻速率。由于这种差异，凹口是 形成在各个栅电极10p，40n和40p的侧表面的底部。

公开(公告)号：US20040043549A1

公开(公告)日：2004-03-04

申请号：US10452309

申请日：2003-06-03

申请人： Renesas Technology Corp.

发明人： Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC分类号： H01L021/336

CPC分类号： H01L21/28052 ,  H01L21/28044 ,  H01L21/28114 ,  H01L21/28518 ,  H01L21/32155 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665

摘要： A semiconductor device which provides for reduction of a gate length and a resistance of a gate electrode of a MOS transistor, and a manufacturing method thereof, are provided. In forming a gate electrode (4), ions are implanted at a dose of 6null1015/cm2 or larger and annealing is performed, so that an upper portion of the gate electrode (4) expands. A silicide layer (4b) formed in the upper portion of the gate electrode (4) has a shape with an upper portion thereof being wider than a bottom portion thereof in section taken along a channel length direction. On the other hand, a polysilicon layer 4a has a shape with upper and bottom portions thereof having the substantially same width in section taken along a channel length direction, like the conventional structure. Thus, even when the width of the polysilicon layer (4a) is reduced to reduce a gate length, the width of the silicide layer (4b) is kept larger than the gate length, to prevent agglomeration of silicide in the silicide layer (4b).

摘要翻译： 提供了一种用于降低MOS晶体管的栅极长度和栅电极的电阻的半导体器件及其制造方法。 在形成栅电极（4）时，以6×10 15 / cm 2或更大的剂量注入离子，进行退火，使得栅电极（4）的上部扩大。 形成在栅电极（4）的上部的硅化物层（4b）具有沿着沟道长度方向截取的其上部比其底部部分更宽的形状。 另一方面，像现有的结构那样，多晶硅层4a具有其上部和底部具有沿着沟道长度方向截取的截面宽度基本相同的形状。 因此，即使当多晶硅层（4a）的宽度减小以减小栅极长度时，硅化物层（4b）的宽度保持大于栅极长度，以防止硅化物层（4b）中的硅化物的聚集， 。

公开(公告)号：US20040101999A1

公开(公告)日：2004-05-27

申请号：US10442226

申请日：2003-05-21

申请人： Renesas Technology Corp.

发明人： Hidekazu Oda ,  Hirokazu Sayama ,  Kazunobu Ohta ,  Kouhei Sugihara

IPC分类号： H01L021/00 ,  H01L021/336 ,  H01L021/8234 ,  H01L021/425

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/6659

摘要： A method of manufacturing a semiconductor device is provided which can suppress leakage current increases by making into silicide. Impurity that suppresses silicide formation reaction (suppression impurity), such as germanium, is introduced into source/drain regions (16, 36) from their upper surfaces. In the source/drain regions (16, 36), a region shallower than a region where the suppression impurity is distributed (50) is made into silicide, so that a silicide film (51) is formed in the source/drain regions (16, 36). Thus, by making the region shallower than the region (50) into silicide, it is possible to suppress that silicide formation reaction extends to the underside of the region to be made into silicide. This enables to reduce the junction leakage between the source/drain regions (16, 36) and a well region.

摘要翻译： 提供一种制造半导体器件的方法，其可以通过制造硅化物来抑制泄漏电流的增加。 抑制硅化物形成反应（抑制杂质）如锗的杂质从其上表面引入源/漏区（16,36）。 在源极/漏极区域（16,36）中，将比抑制杂质分布区域浅的区域（50）制成硅化物，使得在源极/漏极区域（16）中形成硅化物膜（51） ，36）。 因此，通过使区域（50）的区域比硅化物更浅，可以抑制硅化物形成反应延伸到要制成硅化物的区域的下侧。 这使得能够减少源极/漏极区域（16,36）与阱区域之间的结漏电。

公开(公告)号：US20040097030A1

公开(公告)日：2004-05-20

申请号：US10620379

申请日：2003-07-17

申请人： Renesas Technology Corp.

发明人： Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC分类号： H01L021/8238

CPC分类号： H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

摘要： A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000null C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.

摘要翻译： 在硅衬底（10）上设置用于形成nMOS晶体管的非单晶硅的栅极绝缘膜（13）和栅电极（14）。 使用栅极（14）作为掩模，注入具有相对较大质量数（70以上）的诸如As离子或Sb离子的n型掺杂剂，以形成nMOS晶体管的源极/漏极区域，由此， 栅电极（14）非晶化。 随后，提供氧化硅膜（40）以比栅电极（14）再结晶发生的温度小的温度覆盖栅电极（14）。 此后，在约1000℃的温度下进行热处理，由此在栅电极（14）上施加高的压缩残余应力，并且对栅电极（14）下的沟道区域施加高的拉伸应力。 结果，增强了nMOS晶体管的载流子迁移率。

公开(公告)号：US20040087118A1

公开(公告)日：2004-05-06

申请号：US10608154

申请日：2003-06-30

申请人： Renesas Technology Corp. ,  Ion Engineering Research Institute, Corporation ,  Natsuro Tsubouchi

发明人： Shigeto Maegawa ,  Takashi Ipposhi ,  Kazunobu Ohta ,  Yasuo Inoue ,  Masanobu Kohara ,  Takashi Eura ,  Natsuro Tsubouchi

IPC分类号： H01L021/425 ,  H01L021/26 ,  H01L021/42 ,  H01L021/22 ,  H01L021/38 ,  H01L021/324 ,  H01L021/477

CPC分类号： H01L21/268 ,  H01L21/2652 ,  H01L21/28518 ,  H01L29/6659

摘要： Activation of impurities is achieved without involving creation of a crystal defect or deformation by using phonon absorption. A laser beam (42) having a wavelength in a range of 16 to 17 nullm is irradiated onto silicon, to cause phonon absorption. Before an energy supplied from the laser beam (42) diffuses around a portion which is irradiated with the laser beam (42), solid phase epitaxy in the portion finishes. Accordingly, crystallization occurs only in the portion which is irradiated with the laser beam (42), and does not occur in a portion which is not irradiated with the laser beam (42). Hence, heat is not excessively absorbed. Also, local phase change such as melting and solidification is not caused.

摘要翻译： 实现杂质的活化而不涉及通过使用声子吸收产生晶体缺陷或变形。 将具有16至17μm波长范围的激光束（42）照射到硅上以引起声子吸收。 在从激光束（42）供给的能量在激光束（42）的一部分附近扩散之前，该部分的固相外延结束。 因此，仅在被激光束（42）照射的部分中发生结晶，不会发生在不被激光束（42）照射的部分。 因此，热量不会被过度吸收。 此外，不会引起局部相变，如熔化和凝固。