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公开(公告)号：US20040157418A1
公开(公告)日：2004-08-12
申请号：US10722867
申请日：2003-11-26
IPC分类号： H01L021/425
CPC分类号： H01L21/823878 , H01L21/823892
摘要： A method of forming retrograde n-wells and p-wells. A first mask is formed on the substrate and the n-well implants are carried out. Then the mask is thinned, and a deep p implant is carried out with the thinned n-well mask in place. This prevents Vt shifts in FETs formed in the n-well adjacent the nwell-pwell interface. The thinned mask is then removed, a p-well mask is put in place, and the remainder of the p-well implants are carried out.
摘要翻译： 形成逆行n井和p井的方法。 在基板上形成第一掩模，并执行n阱注入。 然后将掩模变薄，并用较薄的n面罩进行深度p植入。 这防止了在n阱中形成的在n阱中形成的FET的Vt偏移。 然后去除变薄的掩模，将p-阱掩模放置就位，并且执行其余的p阱注入。
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公开(公告)号：US20040001376A1
公开(公告)日：2004-01-01
申请号：US10064302
申请日：2002-07-01
IPC分类号： G11C029/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/5006
摘要： A method and structure for a test structure that has an array of cells connected together by conductive lines. The conductive lines connect the cells together as if they were a single cell. The conductive lines can include common word line; a common bit line; a common bit line complement line, a common N-well voltage line, a common interior ground line, a common interior voltage line, and/or a common ground line.
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公开(公告)号：US20030197227A1
公开(公告)日：2003-10-23
申请号：US10063406
申请日：2002-04-19
IPC分类号： H01L029/76 , H01L021/76 , H01L031/062
CPC分类号： H01L21/823878 , H01L21/823892
摘要： A method of forming retrograde n-wells and p-wells. A first mask is formed on the substrate and the n-well implants are carried out. Then the mask is thinned, and a deep p implant is carried out with the thinned n-well mask in place. This prevents Vt shifts in FETs formed in the n-well adjacent the nwell-pwell interface. The thinned mask is then removed, a p-well mask is put in place, and the remainder of the p-well implants are carried out.
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