DEVICE MODELING FOR PROXIMITY EFFECTS
    1.
    发明申请
    DEVICE MODELING FOR PROXIMITY EFFECTS 有权
    近似效应的设备建模

    公开(公告)号:US20040034517A1

    公开(公告)日:2004-02-19

    申请号:US10248853

    申请日:2003-02-25

    IPC分类号: G06F017/50

    摘要: A method for calibrating a software model for a given structure of interest for a variable imposed by an adjacent structure. First determine the spatial extent of the variable imposed by the adjacent structure. Then assign a value to the spatial extent, which varies as a function of distance from the adjacent structure to the given structure. Finally, attach that value to the model of the given structure.

    摘要翻译: 一种用于校正由相邻结构施加的变量的给定感兴趣结构的软件模型的方法。 首先确定相邻结构施加的变量的空间范围。 然后为空间范围分配一个值,该空间范围随着从相邻结构到给定结构的距离的函数而变化。 最后,将该值附加到给定结构的模型中。

    STI stress modification by nitrogen plasma treatment for improving performance in small width devices
    5.
    发明申请
    STI stress modification by nitrogen plasma treatment for improving performance in small width devices 有权
    通过氮等离子体处理进行STI应力改进,以改善小宽度器件的性能

    公开(公告)号:US20040238914A1

    公开(公告)日:2004-12-02

    申请号:US10751831

    申请日:2004-01-05

    IPC分类号: H01L029/00

    摘要: A method for modulating the stress caused by bird beak formation of small width devices by a nitrogen plasma treatment. The nitrogen plasma process forms a nitride liner about the trench walls that serves to prevent the formation of bird beaks in the isolation region during a subsequent oxidation step. In one embodiment, the plasma nitridation process occurs after trench etching, but prior to trench fill. In yet another embodiment, the plasma nitridation process occurs after trench fill. In yet another embodiment, a block mask is formed over predetermined active areas of the etched substrate prior to the plasma nitridation process. This embodiment is used in protecting the PFET device area from the plasma nitridation process thereby providing a means to form a PFET device area in which stress caused by bird beak formation increases the device performance of the PFET.

    摘要翻译: 一种通过氮等离子体处理调节小宽度装置的鸟嘴形成引起的应力的方法。 氮等离子体工艺形成围绕沟槽壁的氮化物衬垫,其用于在随后的氧化步骤期间防止在隔离区中形成鸟嘴。 在一个实施例中,等离子体氮化处理发生在沟槽蚀刻之后,但在沟槽填充之前。 在另一个实施例中,等离子体氮化处理发生在沟槽填充之后。 在另一个实施例中,在等离子体氮化处理之前,在蚀刻的衬底的预定有效区域上形成块掩模。 该实施例用于保护PFET器件区域免受等离子体氮化处理,从而提供形成PFET器件区域的装置,其中由鸟嘴形成引起的应力增加了PFET的器件性能。

    STI STRESS MODIFICATION BY NITROGEN PLASMA TREATMENT FOR IMPROVING PERFORMANCE IN SMALL WIDTH DEVICES
    6.
    发明申请
    STI STRESS MODIFICATION BY NITROGEN PLASMA TREATMENT FOR IMPROVING PERFORMANCE IN SMALL WIDTH DEVICES 失效
    用于改善小宽度装置性能的硝基等离子体处理的STI应力变化

    公开(公告)号:US20040242010A1

    公开(公告)日:2004-12-02

    申请号:US10250047

    申请日:2003-05-30

    IPC分类号: H01L021/302

    摘要: A method for modulating the stress caused by bird beak formation of small width devices by a nitrogen plasma treatment. The nitrogen plasma process forms a nitride liner about the trench walls that serves to prevent the formation of bird beaks in the isolation region during a subsequent oxidation step. In one embodiment, the plasma nitridation process occurs after trench etching, but prior to trench fill. In yet another embodiment, the plasma nitridation process occurs after trench fill. In yet another embodiment, a block mask is formed over predetermined active areas of the etched substrate prior to the plasma nitridation process. This embodiment is used in protecting the PFET device area from the plasma nitridation process thereby providing a means to form a PFET device area in which stress caused by bird beak formation increases the device performance of the PFET.

    摘要翻译: 一种通过氮等离子体处理调节小宽度装置的鸟嘴形成引起的应力的方法。 氮等离子体工艺形成围绕沟槽壁的氮化物衬垫,其用于在随后的氧化步骤期间防止在隔离区中形成鸟嘴。 在一个实施例中,等离子体氮化处理发生在沟槽蚀刻之后,但在沟槽填充之前。 在另一个实施例中,等离子体氮化处理发生在沟槽填充之后。 在另一个实施例中,在等离子体氮化处理之前,在蚀刻的衬底的预定有效区域上形成块掩模。 该实施例用于保护PFET器件区域免受等离子体氮化处理,从而提供形成PFET器件区域的装置,其中由鸟嘴形成引起的应力增加了PFET的器件性能。

    CMOS device having retrograde n-well and p-well
    7.
    发明申请
    CMOS device having retrograde n-well and p-well 失效
    CMOS器件具有逆向n阱和p阱

    公开(公告)号:US20040157418A1

    公开(公告)日:2004-08-12

    申请号:US10722867

    申请日:2003-11-26

    IPC分类号: H01L021/425

    摘要: A method of forming retrograde n-wells and p-wells. A first mask is formed on the substrate and the n-well implants are carried out. Then the mask is thinned, and a deep p implant is carried out with the thinned n-well mask in place. This prevents Vt shifts in FETs formed in the n-well adjacent the nwell-pwell interface. The thinned mask is then removed, a p-well mask is put in place, and the remainder of the p-well implants are carried out.

    摘要翻译: 形成逆行n井和p井的方法。 在基板上形成第一掩模,并执行n阱注入。 然后将掩模变薄,并用较薄的n面罩进行深度p植入。 这防止了在n阱中形成的在n阱中形成的FET的Vt偏移。 然后去除变薄的掩模,将p-阱掩模放置就位,并且执行其余的p阱注入。

    Method and structure to reduce CMOS inter-well leakage
    8.
    发明申请
    Method and structure to reduce CMOS inter-well leakage 有权
    减少CMOS井间泄漏的方法和结构

    公开(公告)号:US20020135024A1

    公开(公告)日:2002-09-26

    申请号:US09803117

    申请日:2001-03-10

    IPC分类号: H01L029/76 H01L021/8238

    摘要: A method of forming a semiconductor device with improved leakage control, includes: providing a semiconductor substrate; forming a trench in the substrate; forming a leakage stop implant in the substrate under the bottom of the trench and under and aligned to a sidewall of the trench; filling the trench with an insulator; and forming an N-well (or a P-well) in the substrate adjacent to and in contact with an opposite sidewall of the trench, the N-well (or the N-well) extending under the trench and forming an upper portion of an isolation junction with the leakage stop implant, the upper portion of the isolation junction located entirely under the trench. The leakage control implant is self-aligned to the trench sidewalls.

    摘要翻译: 一种形成具有改进的泄漏控制的半导体器件的方法,包括:提供半导体衬底; 在衬底中形成沟槽; 在沟槽的底部下方的衬底中形成泄漏停止注入,并在沟槽的侧壁下方并对齐; 用绝缘体填充沟槽; 以及在所述衬底中与所述沟槽的相对侧壁相邻并与之相接触的衬底中形成N阱(或P阱),所述N阱(或所述N阱)在所述沟槽下方延伸并形成所述沟槽的上部 与泄漏停止注入的隔离结,隔离结的上部完全位于沟槽下方。 泄漏控制植入物与沟槽侧壁自对准。