公开(公告)号：US09437457B2

公开(公告)日：2016-09-06

申请号：US14015012

申请日：2013-08-30

Applicant: MediaTek Inc.

Inventor： Wen-Sung Hsu ,  Ming-Chieh Lin ,  Ta-Jen Yu

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/4828 ,  H01L21/481 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11912 ,  H01L2224/16238 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8146 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01109 ,  H01L2924/012

Abstract: According to an embodiment of the present invention, a chip package is provided. The chip package includes: a patterned conducting plate having a plurality of conducting sections electrically separated from each other; a plurality of conducting pads disposed on an upper surface of the patterned conducting plate; a chip disposed on the conducting pads; a plurality of conducting bumps disposed on a lower surface of the patterned conducting plate, wherein each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; and an insulating support layer partially surrounding the conducting bumps.

Abstract translation: 根据本发明的实施例，提供了一种芯片封装。 芯片封装包括：图案化导电板，其具有彼此电分离的多个导电部分; 设置在所述图案化导电板的上表面上的多个导电焊盘; 设置在导电垫上的芯片; 设置在所述图案化导电板的下表面上的多个导电凸块，其中每个所述导电凸块电连接到所述图案化导电板的相应一个导电部分; 以及部分地围绕导电凸块的绝缘支撑层。

公开(公告)号：US09536846B2

公开(公告)日：2017-01-03

申请号：US14526073

申请日：2014-10-28

Applicant: SK hynix Inc.

Inventor： Jin Woo Park ,  Sung Su Park ,  Bae Yong Kim

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L21/683

CPC classification number: H01L24/05 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/034 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/051 ,  H01L2224/05138 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/119 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01014 ,  H01L2924/012

Abstract: A semiconductor device includes a chip body having an uneven surface including at least two regions at different levels from one another, a through electrode penetrating the chip body and having an end which is exposed by the uneven surface of the chip body, a passivation layer disposed on the uneven surface of the chip body, and a bump disposed on the passivation layer and the exposed end of the through electrode and overlapping with the uneven surface of the chip body.

Abstract translation: 一种半导体器件包括：芯片本体，具有包括彼此不同的至少两个区域的不平坦表面;穿透芯片本体并具有由芯片体的不平坦表面露出的端部的贯通电极，设置有钝化层 并且设置在钝化层和通孔的露出端上并与芯片体的不平坦表面重叠的凸起。

公开(公告)号：US20160020184A1

公开(公告)日：2016-01-21

申请号：US14526073

申请日：2014-10-28

Applicant: SK hynix Inc.

Inventor： Jin Woo PARK ,  Sung Su PARK ,  Bae Yong KIM

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L24/05 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/034 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/051 ,  H01L2224/05138 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/119 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01014 ,  H01L2924/012

Abstract: A semiconductor device includes a chip body having an uneven surface including at least two regions at different levels from one another, a through electrode penetrating the chip body and having an end which is exposed by the uneven surface of the chip body, a passivation layer disposed on the uneven surface of the chip body, and a bump disposed on the passivation layer and the exposed end of the through electrode and overlapping with the uneven surface of the chip body.

Abstract translation: 一种半导体器件包括：芯片本体，具有包括彼此不同的至少两个区域的不平坦表面;穿透芯片本体并具有由芯片体的不平坦表面露出的端部的贯通电极，设置有钝化层 并且设置在钝化层和通孔的露出端上并与芯片体的不平坦表面重叠的凸起。

公开(公告)号：US10074581B2

公开(公告)日：2018-09-11

申请号：US15225927

申请日：2016-08-02

Applicant: MediaTek Inc.

Inventor： Wen-Sung Hsu ,  Ming-Chieh Lin ,  Ta-Jen Yu

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16238 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8146 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01109 ,  H01L2924/012

Abstract: A chip package includes a patterned conducting plate having a plurality of conducting sections electrically separated from each other, a plurality of conducting pads disposed on an upper surface of the patterned conducting plate, wherein a recess extending from a surface of one of the conducting pads towards an inner portion of the corresponding one of the conducting pads, a chip disposed on the conducting pads, a plurality of conducting bumps disposed on a lower surface of the patterned conducting plate, wherein each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate, and an insulating support layer partially surrounding the conducting bumps.

公开(公告)号：US20160343632A1

公开(公告)日：2016-11-24

申请号：US15225927

申请日：2016-08-02

Applicant: MediaTek Inc.

Inventor： Wen-Sung HSU ,  Ming-Chieh LIN ,  Ta-Jen YU

IPC: H01L23/31 ,  H01L23/00

CPC classification number: H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16238 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8146 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01109 ,  H01L2924/012

Abstract: A chip package includes a patterned conducting plate having a plurality of conducting sections electrically separated from each other, a plurality of conducting pads disposed on an upper surface of the patterned conducting plate, wherein a recess extending from a surface of one of the conducting pads towards an inner portion of the corresponding one of the conducting pads, a chip disposed on the conducting pads, a plurality of conducting bumps disposed on a lower surface of the patterned conducting plate, wherein each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate, and an insulating support layer partially surrounding the conducting bumps.

Abstract translation: 芯片封装包括具有彼此电分离的多个导电部分的图案化导电板，设置在图案化导电板的上表面上的多个导电焊盘，其中从一个导电焊盘的表面向着 相应的一个导电焊盘的内部部分，设置在导电焊盘上的芯片，设置在图案化导电板的下表面上的多个导电凸块，其中每个导电凸块电连接到 图案化导电板的导电部分和部分地围绕导电凸块的绝缘支撑层。

公开(公告)号：US09373526B2

公开(公告)日：2016-06-21

申请号：US14556542

申请日：2014-12-01

Applicant: MediaTek Inc.

Inventor： Wen-Sung Hsu ,  Ming-Chieh Lin ,  Ta-Jen Yu

IPC: H01L21/44 ,  H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/4828 ,  H01L21/481 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11912 ,  H01L2224/16238 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8146 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01109 ,  H01L2924/012

Abstract: According to an embodiment of the present invention, a method for forming a chip package is provided. The method includes: providing a conducting plate, wherein a plurality of conducting pads are disposed on an upper surface of the conducting plate; forming a plurality of conducting bumps on a lower surface of the conducting plate; patterning the conducting plate by removing a portion of the conducting plate, wherein the patterned conducting plate has a plurality of conducting sections electrically insulated from each other, and each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; forming an insulating support layer to partially surround the conducting bumps; and disposing a chip on the conducting pads.

Abstract translation: 根据本发明的实施例，提供了一种用于形成芯片封装的方法。 该方法包括：提供导电板，其中多个导电焊盘设置在导电板的上表面上; 在导电板的下表面上形成多个导电凸块; 通过去除导电板的一部分来图案化导电板，其中图案化的导电板具有彼此电绝缘的多个导电部分，并且每个导电凸块电连接到图案化的导电部分的相应一个导电部分 导电板 形成绝缘支撑层以部分地包围所述导电凸块; 并将芯片设置在导电焊盘上。

公开(公告)号：US20150087115A1

公开(公告)日：2015-03-26

申请号：US14556542

申请日：2014-12-01

Applicant: MediaTek Inc.

Inventor： Wen-Sung HSU ,  Ming-Chieh LIN ,  Ta-Jen YU

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L21/4828 ,  H01L21/481 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11912 ,  H01L2224/16238 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8146 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01109 ,  H01L2924/012

Abstract: According to an embodiment of the present invention, a method for forming a chip package is provided. The method includes: providing a conducting plate, wherein a plurality of conducting pads are disposed on an upper surface of the conducting plate; forming a plurality of conducting bumps on a lower surface of the conducting plate; patterning the conducting plate by removing a portion of the conducting plate, wherein the patterned conducting plate has a plurality of conducting sections electrically insulated from each other, and each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; forming an insulating support layer to partially surround the conducting bumps; and disposing a chip on the conducting pads.

Abstract translation: 根据本发明的实施例，提供了一种用于形成芯片封装的方法。 该方法包括：提供导电板，其中多个导电焊盘设置在导电板的上表面上; 在导电板的下表面上形成多个导电凸块; 通过去除导电板的一部分来图案化导电板，其中图案化的导电板具有彼此电绝缘的多个导电部分，并且每个导电凸块电连接到图案化的导电部分的相应一个导电部分 导电板 形成绝缘支撑层以部分地包围所述导电凸块; 并将芯片设置在导电焊盘上。

公开(公告)号：US20150061117A1

公开(公告)日：2015-03-05

申请号：US14015012

申请日：2013-08-30

Applicant: MediaTek Inc.

Inventor： Wen-Sung HSU ,  Ming-Chieh LIN ,  Ta-Jen YU

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L21/4828 ,  H01L21/481 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11912 ,  H01L2224/16238 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8146 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01109 ,  H01L2924/012

Abstract: According to an embodiment of the present invention, a chip package is provided. The chip package includes: a patterned conducting plate having a plurality of conducting sections electrically separated from each other; a plurality of conducting pads disposed on an upper surface of the patterned conducting plate; a chip disposed on the conducting pads; a plurality of conducting bumps disposed on a lower surface of the patterned conducting plate, wherein each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; and an insulating support layer partially surrounding the conducting bumps.

Abstract translation: 根据本发明的实施例，提供了一种芯片封装。 芯片封装包括：图案化导电板，其具有彼此电分离的多个导电部分; 设置在所述图案化导电板的上表面上的多个导电焊盘; 设置在导电垫上的芯片; 设置在所述图案化导电板的下表面上的多个导电凸块，其中每个所述导电凸块电连接到所述图案化导电板的相应一个导电部分; 以及部分地围绕导电凸块的绝缘支撑层。

公开(公告)号：US20090079042A1

公开(公告)日：2009-03-26

申请号：US11858911

申请日：2007-09-21

Applicant: Jim Clatterbaugh ,  Hassan Tanbakuchi ,  Matthew R. Richter ,  Michael B. Whitener

Inventor： Jim Clatterbaugh ,  Hassan Tanbakuchi ,  Matthew R. Richter ,  Michael B. Whitener

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/85 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/05553 ,  H01L2224/45012 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45016 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45644 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/48475 ,  H01L2224/48479 ,  H01L2224/48499 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49426 ,  H01L2224/83099 ,  H01L2224/85045 ,  H01L2224/85051 ,  H01L2224/85099 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/2076 ,  H01L2924/30107 ,  H01L2924/0103 ,  H01L2924/01004 ,  H01L2924/012 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2224/45099 ,  H01L2924/01006 ,  H01L2224/85399 ,  H01L2224/05599 ,  H01L2924/206

Abstract: A microcircuit has a node thereon. A center conductor is electrically connected to the node and the center conductor has a length to minimum radius ratio of at least 50. A method of for providing electrical interconnections in a microcircuit, comprises the steps of depositing conductive bumps on the microcircuit; and aligning and bonding a center conductor to the conductive bumps, the center conductor having a first end and a second end, and the center conductor having a length to minimum radius ratio of at least 50.

Abstract translation: 微电路上有一个节点。 中心导体电连接到节点，中心导体的长度与最小半径比至少为50.一种用于在微电路中提供电互连的方法包括以下步骤：在微电路上沉积导电凸块; 以及将中心导体对准和结合到所述导电凸块，所述中心导体具有第一端和第二端，所述中心导体的长度与最小半径比至少为50。