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公开(公告)号：US11990448B2
公开(公告)日：2024-05-21
申请号：US17025709
申请日：2020-09-18
Applicant: Intel Corporation
Inventor： Feras Eid , Adel A. Elsherbini , Aleksandar Aleksov , Shawna M. Liff , Johanna M. Swan
IPC: H01L25/065 , H01L23/00
CPC classification number: H01L25/0655 , H01L24/06 , H01L24/08 , H01L24/09 , H01L24/17 , H01L24/29 , H01L24/30 , H01L25/0652 , H01L2224/08225 , H01L2224/09177 , H01L2224/81
Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.
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公开(公告)号：US11710727B2
公开(公告)日：2023-07-25
申请号：US17003694
申请日：2020-08-26
Applicant: KIOXIA CORPORATION
Inventor： Nobuaki Okada , Tetsuaki Utsumi
CPC classification number: H01L25/18 , G11C16/30 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/09 , G11C16/0483 , H01L2224/03452 , H01L2224/0557 , H01L2224/05572 , H01L2224/08145 , H01L2224/09133 , H01L2224/09134 , H01L2224/09177 , H01L2224/09181 , H01L2924/1431 , H01L2924/14511
Abstract: A semiconductor storage device includes first and second chips and first and second power supply electrodes. The first chip includes conductive layers arranged in a first direction, a semiconductor pillar extending in the first direction and facing the conductive layers, first contacts extending in the first direction and connected to the conductive layers, second contacts extending in the first direction and connected to a first power supply electrode, third contacts extending in the first direction, facing the second contacts in a direction crossing the first direction, and connected to the second power supply electrode, and first bonding electrodes connected to the first contacts. The second chip includes a semiconductor substrate, transistors provided on the semiconductor substrate, fourth contacts connected to the transistors, and second bonding electrodes connected to the fourth contacts. The first and second chips are bonded together so that respective first and second bonding electrodes are connected together.
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公开(公告)号：US12132040B2
公开(公告)日：2024-10-29
申请号：US18330258
申请日：2023-06-06
Applicant: Kioxia Corporation
Inventor： Nobuaki Okada , Tetsuaki Utsumi
CPC classification number: H01L25/18 , G11C16/30 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/09 , G11C16/0483 , H01L2224/03452 , H01L2224/0557 , H01L2224/05572 , H01L2224/08145 , H01L2224/09133 , H01L2224/09134 , H01L2224/09177 , H01L2224/09181 , H01L2924/1431 , H01L2924/14511
Abstract: A semiconductor storage device includes first and second chips and first and second power supply electrodes. The first chip includes conductive layers arranged in a first direction, a semiconductor pillar extending in the first direction and facing the conductive layers, first contacts extending in the first direction and connected to the conductive layers, second contacts extending in the first direction and connected to a first power supply electrode, third contacts extending in the first direction, facing the second contacts in a direction crossing the first direction, and connected to the second power supply electrode, and first bonding electrodes connected to the first contacts. The second chip includes a semiconductor substrate, transistors provided on the semiconductor substrate, fourth contacts connected to the transistors, and second bonding electrodes connected to the fourth contacts. The first and second chips are bonded together so that respective first and second bonding electrodes are connected together.
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Patent Agency Ranking
公开(公告)号：US20230395536A1
公开(公告)日：2023-12-07
申请号：US18451857
申请日：2023-08-18
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Naohide TOMITA , Hiroshi NISHIKAWA
IPC: H01L23/66 , H01L23/498 , H01L23/538 , H01L23/522 , H01L23/48 , H01L23/00
CPC classification number: H01L23/66 , H01L23/49805 , H01L23/49838 , H01L23/5389 , H01L23/5226 , H01L23/481 , H01L24/16 , H01L24/08 , H01L24/09 , H01L2223/6677 , H01L2223/6616 , H01L2223/6655 , H01L2224/16145 , H01L2224/08112 , H01L2224/0903 , H01L2224/09177
Abstract: A radio frequency module includes a mounting substrate including a first main surface and a second main surface opposite to the first main surface. A first electronic component is disposed on the first main surface of the mounting substrate. A second electronic component is disposed on the second main surface of the mounting substrate. A plurality of connection terminals are disposed on the second main surface of the mounting substrate. A wiring layer faces the second main surface of the mounting substrate. The wiring layer includes a plurality of external connection electrodes, each connected to at least one of the second electronic component and the plurality of connection terminals. At least one of the plurality of external connection electrodes overlaps the second electronic component when viewed in plan in a thickness direction of the substrate.
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公开(公告)号：US20240274576A1
公开(公告)日：2024-08-15
申请号：US18632919
申请日：2024-04-11
Applicant: Intel Corporation
Inventor： Feras Eid , Adel A. Elsherbini , Aleksandar Aleksov , Shawna M. Liff , Johanna M. Swan
IPC: H01L25/065 , H01L23/00
CPC classification number: H01L25/0655 , H01L24/06 , H01L24/08 , H01L24/09 , H01L24/17 , H01L24/29 , H01L24/30 , H01L25/0652 , H01L2224/08225 , H01L2224/09177 , H01L2224/81
Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region including metal contacts that are distributed non-uniformly. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact.
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公开(公告)号：US20240222322A1
公开(公告)日：2024-07-04
申请号：US18240041
申请日：2023-08-30
Applicant: SAMSUNG ELECRTONICS CO., LTD.
Inventor： Hanmin Nam , Jeunghwan Park , Pansuk Kwak
CPC classification number: H01L25/0652 , G11C5/063 , H01L24/08 , H01L24/09 , H10B41/27 , H10B41/41 , H10B43/27 , H10B43/40 , H10B80/00 , H01L24/80 , H01L2224/08145 , H01L2224/0913 , H01L2224/09177 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/1438
Abstract: A non-volatile memory device includes: a memory cell region including: a plurality of bit lines each extending in a first direction; and a plurality of upper bonding pads; and a peripheral circuit region including: a page buffer circuit; a plurality of lower bonding pads provided above the page buffer circuit and each connected to a respective one of the plurality of upper bonding pads; and a plurality of through-wiring lines each extending in the first direction. The plurality of lower bonding pads includes: first lower bonding pads, which are provided in a first line extending in the first direction; and second lower bonding pads, which are provided in a second line extending in the first direction. The plurality of through-wiring lines includes at least one first through-wiring line extending between the first line and the second line and extending across the page buffer circuit.
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公开(公告)号：US20180096970A1
公开(公告)日：2018-04-05
申请号：US15282855
申请日：2016-09-30
Applicant: Klaus Reingruber , Andreas Wolter , Georg Seidemann , Thomas Wagner , Bernd Waidhas
Inventor： Klaus Reingruber , Andreas Wolter , Georg Seidemann , Thomas Wagner , Bernd Waidhas
IPC: H01L25/065 , H01L23/31 , H01L23/00
CPC classification number: H01L24/06 , H01L23/3128 , H01L24/13 , H01L24/14 , H01L24/17 , H01L25/117 , H01L25/50 , H01L2224/02311 , H01L2224/0237 , H01L2224/02379 , H01L2224/04105 , H01L2224/06132 , H01L2224/06134 , H01L2224/09177 , H01L2224/11334 , H01L2224/12105 , H01L2224/13024 , H01L2224/1403 , H01L2224/14051 , H01L2224/16145 , H01L2224/1703 , H01L2224/17051 , H01L2224/73204 , H01L2225/1058 , H01L2225/1064
Abstract: A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer 108, and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer 108. The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.
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公开(公告)号：US20180045885A1
公开(公告)日：2018-02-15
申请号：US15457637
申请日：2017-03-13
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Arturo Luigi CANALI , Luigi VERGA , Luca MAGGI
IPC: G02B6/12 , H01L23/538 , H01L23/00 , H01L25/00 , H01L25/065
CPC classification number: G02B6/12002 , G02B2006/12147 , H01L23/5381 , H01L24/09 , H01L25/0657 , H01L25/167 , H01L25/50 , H01L27/14634 , H01L2224/0401 , H01L2224/09177 , H01L2224/16145 , H01L2224/16235 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81191 , H01L2224/81203 , H01L2224/81815 , H01L2224/92125 , H01L2224/92225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06534 , H01L2225/06548 , H01L2225/06562 , H01L2924/14 , H01L2924/15313 , H01L2924/00
Abstract: A method of manufacturing semiconductor devices includes: coupling first and the second substrates by coupling a back surface of the second substrate with a front surface of the first substrate, thereby producing a step-like structure, with an uncovered portion of the front surface of the first substrate left uncovered by the second substrate coupling a first integrated circuit with the uncovered portion of the front surface of the first substrate; and coupling a second integrated circuit with the second substrate and the first integrated circuit by arranging the second integrated circuit extending bridge—like between the second substrate and the first integrated circuit.
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