公开(公告)号：US20240222322A1

公开(公告)日：2024-07-04

申请号：US18240041

申请日：2023-08-30

Applicant: SAMSUNG ELECRTONICS CO., LTD.

Inventor： Hanmin Nam ,  Jeunghwan Park ,  Pansuk Kwak

IPC: H01L25/065 ,  G11C5/06 ,  H01L23/00 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40 ,  H10B80/00

CPC classification number: H01L25/0652 ,  G11C5/063 ,  H01L24/08 ,  H01L24/09 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40 ,  H10B80/00 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/0913 ,  H01L2224/09177 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1438

Abstract: A non-volatile memory device includes: a memory cell region including: a plurality of bit lines each extending in a first direction; and a plurality of upper bonding pads; and a peripheral circuit region including: a page buffer circuit; a plurality of lower bonding pads provided above the page buffer circuit and each connected to a respective one of the plurality of upper bonding pads; and a plurality of through-wiring lines each extending in the first direction. The plurality of lower bonding pads includes: first lower bonding pads, which are provided in a first line extending in the first direction; and second lower bonding pads, which are provided in a second line extending in the first direction. The plurality of through-wiring lines includes at least one first through-wiring line extending between the first line and the second line and extending across the page buffer circuit.