公开(公告)号：US20160218069A1

公开(公告)日：2016-07-28

申请号：US15089200

申请日：2016-04-01

Applicant: FUJITSU SEMICONDUCTOR LIMITED

Inventor： Kazutaka Yoshizawa ,  Taiji Ema ,  Takuya Moriki

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/544 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L22/34 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L23/564 ,  H01L24/05 ,  H01L2223/5446 ,  H01L2223/5448 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05553 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.

公开(公告)号：US20200335148A1

公开(公告)日：2020-10-22

申请号：US16916370

申请日：2020-06-30

Applicant: FUJITSU SEMICONDUCTOR LIMITED

Inventor： Keizo Morita

IPC: G11C11/22 ,  G11C29/50

Abstract: A first pre-sense amplifier connected to reference cells that hold data of logical value “1” via a first bit line outputs a signal that is obtained by delaying a first amplified signal that is obtained by amplifying a voltage of the first bit line when a memory cell is read. A second pre-sense amplifier connected to memory cells via a second bit line generates a second amplified signal by amplifying a voltage of the second bit line when a memory cell is read. The second pre-sense amplifier receives a signal. When a voltage of the signal reaches a threshold or more, the second pre-sense amplifier drops the voltage of the second bit line to a ground potential.

公开(公告)号：US10510824B2

公开(公告)日：2019-12-17

申请号：US15992645

申请日：2018-05-30

Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED

Inventor： Taiji Ema ,  Nobuhiro Misawa ,  Kazuyuki Kumeno ,  Makoto Yasuda

IPC: H01L27/08 ,  H01L49/02 ,  H01L27/06

Abstract: A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration CX. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration CY lower than the concentration CX. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration CX. A sign of a TCR of the second polycrystalline silicon changes at the concentration CY.

公开(公告)号：US20190326386A1

公开(公告)日：2019-10-24

申请号：US16460497

申请日：2019-07-02

Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED

Inventor： Taiji Ema ,  Nobuhiro Misawa ,  Kazuyuki Kumeno ,  Makoto Yasudo

IPC: H01L49/02 ,  H01L27/08

Abstract: A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration CX. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration CY lower than the concentration CX. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration CX. A sign of a TCR of the second polycrystalline silicon changes at the concentration CY.

公开(公告)号：US10250257B2

公开(公告)日：2019-04-02

申请号：US15964359

申请日：2018-04-27

Applicant: Mie Fujitsu Semiconductor Limited

Inventor： Scott E. Thompson ,  Lawrence T. Clark

IPC: H01L25/00 ,  H03K19/00 ,  H03K19/0948 ,  H01L27/088 ,  G11C11/412 ,  H01L27/118 ,  H01L29/10 ,  H01L27/11

Abstract: Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.

公开(公告)号：US20190080967A1

公开(公告)日：2019-03-14

申请号：US16129518

申请日：2018-09-12

Applicant: Mie Fujitsu Semiconductor Limited

Inventor： Scott E. Thompson ,  Damodar R. Thummalapally

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/092 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L29/10 ,  H01L27/11 ,  H01L27/02 ,  H01L21/84 ,  H01L21/8238

Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.

公开(公告)号：US10217838B2

公开(公告)日：2019-02-26

申请号：US15963598

申请日：2018-04-26

Applicant: Mie Fujitsu Semiconductor Limited

Inventor： Dalong Zhao ,  Teymur Bakhishev ,  Lance Scudder ,  Paul E. Gregory ,  Michael Duane ,  U. C. Sridharan ,  Pushkar Ranade ,  Lucian Shifren ,  Thomas Hoffmann

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/283

Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.

公开(公告)号：US10217668B2

公开(公告)日：2019-02-26

申请号：US15398471

申请日：2017-01-04

Applicant: Mie Fujitsu Semiconductor Limited

Inventor： Scott E. Thompson ,  Damodar R. Thummalapally

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/02 ,  H01L27/11 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06

Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.

公开(公告)号：US20190034671A1

公开(公告)日：2019-01-31

申请号：US16036230

申请日：2018-07-16

Applicant: FUJITSU SEMICONDUCTOR LIMITED

Inventor： Takahiko Sato

IPC: G06K7/00 ,  G06K7/10 ,  G06K19/07 ,  H04L1/18 ,  H04B5/00

CPC classification number: G06K7/0008 ,  G06K7/10316 ,  G06K19/0723 ,  H04B5/0062 ,  H04L1/18 ,  H04W4/80

Abstract: A radio communication processor receives data to which identification information is assigned and transmits a response signal indicative of whether or not application processing based on the data is normally performed. An application controller controls the application processing on the basis of the data and detects whether or not the application processing is normally performed. A controller detects on the basis of the identification information that the same data are received in succession due to retransmission, nullifies, when the application controller detects that the application processing based on the data received earlier is normally performed, control of the application processing based on the data received later to be performed by the application controller and instructs the radio communication processor to transmit the response signal which indicates that the application processing is normally performed.

公开(公告)号：US20180261617A1

公开(公告)日：2018-09-13

申请号：US15902335

申请日：2018-02-22

Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED

Inventor： Satoshi Torii ,  Hideaki Matsumura ,  Shu Ishihara

IPC: H01L27/11573 ,  H01L27/1157

CPC classification number: H01L27/11573 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/1157

Abstract: A manufacturing method of a semiconductor device includes: forming a tunnel oxide layer and a charge-storage layer in a region of a flash memory transistor; forming a first oxide film; removing the first oxide film in regions of a first transistor and a second transistor; forming a third oxide film by adding a first oxide layer between a first oxide film and a semiconductor substrate in a region of a third transistor while forming a second oxide film in the regions of the first transistor and the second transistor by oxidation; removing the second oxide film in the region of the first transistor; and forming a fifth oxide film by adding a second oxide layer between the second oxide film and the semiconductor substrate in the region of the second transistor while forming a fourth oxide film in the region of the first transistor by oxidation, and forming a sixth oxide film by adding a third oxide layer between the first oxide layer and the semiconductor substrate in the region of the third transistor.