公开(公告)号：US20110065240A1

公开(公告)日：2011-03-17

申请号：US12578556

申请日：2009-10-13

Applicant: Xu GAO ,  Qingchun He ,  Nan Xu

Inventor： Xu GAO ,  Qingchun He ,  Nan Xu

IPC: H01L21/60 ,  H01L23/495 ,  B21D31/02

CPC classification number: H01L21/4842 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49541 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/48247 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A lead frame and a method of making a lead frame for a semiconductor package. The lead frame is formed by stamping a lead frame material into a desire configuration. The stamped lead frame is then affixed to a support material. When assembling a semiconductor package using the lead frame, during saw singuation, the saw does not have to cut through much lead frame material. Thus, the saw blade does not wear quickly.

Abstract translation: 引线框架和制造用于半导体封装的引线框架的方法。 引线框架通过将引线框架材料冲压成期望配置而形成。 然后将冲压的引线框架固定到支撑材料上。 当使用引线框组装半导体封装时，在锯切时，锯不必切割大量的引线框架材料。 因此，锯片不会很快磨损。

公开(公告)号：US08642395B2

公开(公告)日：2014-02-04

申请号：US12727258

申请日：2010-03-19

Applicant: Zhe Li ,  Qingchun He ,  Guanhua Wang ,  Zhijie Wang ,  Nan Xu

Inventor： Zhe Li ,  Qingchun He ,  Guanhua Wang ,  Zhijie Wang ,  Nan Xu

IPC: H01L21/60 ,  H01L21/56 ,  H01L33/62

CPC classification number: H01L21/565 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49513 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/83099 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/85013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A process for assembling a Chip-On-Lead packaged semiconductor device includes the steps of: mounting and sawing a wafer to provide individual semiconductor dies; performing a first molding operation on a lead frame; depositing epoxy on the lead frame via a screen printing process; attaching one of the singulated dies on the lead frame with the epoxy, where the die attach is done at room temperature; and curing the epoxy in an oven. Throughput improvements may be ascribed to not including a hot die attach process. An optional plasma cleaning step may be performed, which greatly improves wire bonding quality and a second molding quality. In addition, since a first molding operation is performed before the formation of epoxy to avoid the problem of the epoxy hanging in the air, the delamination risk between the epoxy and the die is avoided.

Abstract translation: 芯片引线封装半导体器件的组装方法包括以下步骤：安装和锯切晶片以提供单独的半导体管芯; 在引线框上执行第一模制操作; 通过丝网印刷工艺在引线框架上沉积环氧树脂; 在引线框架上用环氧树脂将一个单模模具附着在模具附着在室温下进行; 并在烘箱中固化环氧树脂。 吞吐量改进可归因于不包括热模附着过程。 可以进行可选的等离子体清洗步骤，这大大提高了引线接合质量和第二成型质量。 此外，由于在形成环氧树脂之前进行第一次成型操作以避免环氧树脂悬挂在空气中的问题，所以避免了环氧树脂和模具之间的脱层危险。

公开(公告)号：US20100248426A1

公开(公告)日：2010-09-30

申请号：US12727258

申请日：2010-03-19

Applicant: Zhe Li ,  Qingchun He ,  Guanhua Wang ,  Zhijie Wang ,  Nan Xu

Inventor： Zhe Li ,  Qingchun He ,  Guanhua Wang ,  Zhijie Wang ,  Nan Xu

IPC: H01L21/78 ,  H01L21/56 ,  H01L21/306

CPC classification number: H01L21/565 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49513 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/83099 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/85013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A process for assembling a Chip-On-Lead packaged semiconductor device includes the steps of: mounting and sawing a wafer to provide individual semiconductor dies; performing a first molding operation on a lead frame; depositing epoxy on the lead frame via a screen printing process; attaching one of the singulated dies on the lead frame with the epoxy, where the die attach is done at room temperature; and curing the epoxy in an oven. Throughput improvements may be ascribed to not including a hot die attach process. An optional plasma cleaning step may be performed, which greatly improves wire bonding quality and a second molding quality. In addition, since a first molding operation is performed before the formation of epoxy to avoid the problem of the epoxy hanging in the air, the delamination risk between the epoxy and the die is avoided.

Abstract translation: 芯片引线封装半导体器件的组装方法包括以下步骤：安装和锯切晶片以提供单独的半导体管芯; 在引线框上执行第一模制操作; 通过丝网印刷工艺在引线框架上沉积环氧树脂; 在引线框架上用环氧树脂将一个单模模具附着在模具附着在室温下进行; 并在烘箱中固化环氧树脂。 吞吐量改进可归因于不包括热模附着过程。 可以进行可选的等离子体清洗步骤，这大大提高了引线接合质量和第二成型质量。 此外，由于在形成环氧树脂之前进行第一次成型操作以避免环氧树脂悬挂在空气中的问题，所以避免了环氧树脂和模具之间的脱层危险。

公开(公告)号：US20160056097A1

公开(公告)日：2016-02-25

申请号：US14556225

申请日：2014-11-30

Applicant: Zhigang Bai ,  Xingshou Pang ,  Nan Xu ,  Jinzhong Yao

Inventor： Zhigang Bai ,  Xingshou Pang ,  Nan Xu ,  Jinzhong Yao

IPC: H01L23/495 ,  H01L21/52 ,  H01L21/78 ,  H01L21/56 ,  H01L21/311 ,  H01L21/3205 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L21/78 ,  H01L21/4842 ,  H01L21/52 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49551 ,  H01L23/49582 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A Quad Flat Non-leaded (QFN) semiconductor die package has a semiconductor die mounted on a die flag of a lead frame. A covers the semiconductor die. The housing has a base and sides. There are electrically conductive mounting feet, each of which has an exposed base portion in the base of the housing and an exposed side portion in the one of the sides of the housing. Bond wires electrically connect electrodes of the semiconductor die to respective ones of the mounting feet.

Abstract translation: 四边形扁平无引线（QFN）半导体管芯封装具有安装在引线框架的管芯标记上的半导体管芯。 A覆盖半导体管芯。 房屋有一个基地和两侧。 存在导电安装脚，每个脚在壳体的基部中具有暴露的基部，并且在壳体的一侧中的暴露的侧部。 接合线将半导体管芯的电极与相应的安装脚电连接。

公开(公告)号：US08115288B2

公开(公告)日：2012-02-14

申请号：US13021716

申请日：2011-02-05

Applicant: Yongsheng Lu ,  Bin Tian ,  Nan Xu ,  Jinzhong Yao ,  Shufeng Zhao

Inventor： Yongsheng Lu ,  Bin Tian ,  Nan Xu ,  Jinzhong Yao ,  Shufeng Zhao

IPC: H01L21/60 ,  H01L23/495

CPC classification number: H01L23/3107 ,  H01L23/49548 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A lead frame for reducing detrimental effects of burr formation includes a lead frame that has leads where a portion of a top surface is removed from a first lead and a portion of a bottom surface is removed from a second lead adjacent to the first lead to reduce spacing between leads while reducing the detrimental effects of burr formation, such as shorting and the like, caused during singulation of a semiconductor device manufactured with the lead frame.

Abstract translation: 用于减少毛刺形成的有害影响的引线框架包括引线框架，其具有引线，其中顶表面的一部分从第一引线移除，并且底表面的一部分从邻近第一引线的第二引线移除以减少 导线之间的间隔，同时减少了由引线框制造的半导体器件的分割期间引起的毛刺形成的不利影响，例如短路等。

公开(公告)号：US20100045554A1

公开(公告)日：2010-02-25

申请号：US12536422

申请日：2009-08-05

Applicant: Nan Xu ,  Wei Huang

Inventor： Nan Xu ,  Wei Huang

IPC: H01Q19/06 ,  H01Q1/38

CPC classification number: H01Q15/0086

Abstract: Metamaterial antennas provide spatially varying electromagnetic coupling that enables impedance matching conditions for different operating frequencies of the MTM antennas so that such antennas can operate at different frequencies for wideband applications, including ultra wideband applications.

Abstract translation: 超材料天线提供空间变化的电磁耦合，其使能针对MTM天线的不同工作频率的阻抗匹配条件，使得这样的天线可以在包括超宽带应用在内的宽带应用的不同频率下工作。

公开(公告)号：US20090295660A1

公开(公告)日：2009-12-03

申请号：US12465571

申请日：2009-05-13

Applicant: Nan Xu ,  Sunil Kumar Rajgopal ,  Norberto Lopez ,  Vaneet Pathak ,  Ajay Gummalla ,  Gregory Poilasne ,  Maha Achour

Inventor： Nan Xu ,  Sunil Kumar Rajgopal ,  Norberto Lopez ,  Vaneet Pathak ,  Ajay Gummalla ,  Gregory Poilasne ,  Maha Achour

IPC: H01Q19/06

CPC classification number: H01Q1/243 ,  H01Q9/0407 ,  H01Q15/0086

Abstract: Antennas for wireless communications based on metamaterial (MTM) structures to arrange one or more antenna sections of an MTM antenna away from one or more other antenna sections of the same MTM antenna so that the antenna sections of the MTM antenna are spatially distributed in a non-planar configuration to provide a compact structure adapted to fit to an allocated space or volume of a wireless communication device, such as a portable wireless communication device.

Abstract translation: 基于超材料（MTM）结构的用于无线通信的天线，用于将MTM天线的一个或多个天线部分远离同一MTM天线的一个或多个其它天线部分，使得MTM天线的天线部分在空间上分布在非 平面配置以提供适于适配于诸如便携式无线通信设备的无线通信设备的分配的空间或卷的紧凑结构。

公开(公告)号：US07056766B2

公开(公告)日：2006-06-06

申请号：US10731831

申请日：2003-12-09

Applicant: Hei Ming Shiu ,  Wai Wong Chow ,  Nan Xu

Inventor： Hei Ming Shiu ,  Wai Wong Chow ,  Nan Xu

IPC: H01L21/44 ,  H01L21/48

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/488 ,  H01L24/05 ,  H01L24/06 ,  H01L24/31 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/056 ,  H01L2224/05644 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48644 ,  H01L2224/48844 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2224/8314 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/85207 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/13111 ,  H01L2924/00011

Abstract: A method of packaging an integrated circuit die (12) includes the steps of forming an array of soft conductive balls (14) in a fixture (30) and flattening opposing sides of the balls. The flattened balls are then transferred from the fixture to a mold masking tape (36). A first side of the IC die is attached to the balls with a die attach adhesive (16) and then wire bonding pads (20) on the die are electrically connected directly to respective balls with wires (22). An encapsulant (24) is formed over the die, the electrical connections, and a top portion of the formed balls. The tape is removed and adjacent, encapsulated dice are separated via saw singulation. The result is an encapsulated IC having a bottom side with exposed balls.

Abstract translation: 封装集成电路管芯（12）的方法包括以下步骤：在夹具（30）中形成软导电球（14）的阵列，并使球的相对侧平坦化。 然后将扁平的球从固定装置转移到模塑胶带（36）。 IC芯片的第一侧通过芯片附接粘合剂（16）附着到球上，然后在芯片上的引线键合焊盘（20）通过导线（22）直接电连接到相应的球。 密封剂（24）形成在模具上，电连接和形成的球的顶部。 胶带被去除并相邻，胶囊通过锯切分离分离。 结果是具有底部具有裸露球的封装IC。

公开(公告)号：US09416002B2

公开(公告)日：2016-08-16

申请号：US14559921

申请日：2014-12-04

Applicant: Nan Xu ,  Xingshou Pang ,  Xuesong Xu

Inventor： Nan Xu ,  Xingshou Pang ,  Xuesong Xu

IPC: H01L29/84 ,  B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00269 ,  B81B7/0058 ,  B81B2201/0264 ,  B81B2207/012 ,  B81C1/00309 ,  G01L19/147 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2224/8592

Abstract: A method for assembling a packaged semiconductor device includes mounting a pressure-sensing die onto a die paddle of a metal lead frame. A pressure-sensitive gel is dispensed into a recess of a lid, and the lead frame is mated with the lid such that the pressure-sensing die is immersed in the pressure-sensitive gel within the recess of the lid.

Abstract translation: 一种用于组装封装的半导体器件的方法包括将压敏感应模具安装到金属引线框架的裸片上。 压敏凝胶被分配到盖的凹部中，并且引线框架与盖子配合，使得压力感测模具浸入到盖的凹部内的压敏凝胶中。

公开(公告)号：US08859336B2

公开(公告)日：2014-10-14

申请号：US13398816

申请日：2012-02-16

Applicant: Junhua Luo ,  Zhigang Bai ,  Nan Xu ,  Jinzhong Yao

Inventor： Junhua Luo ,  Zhigang Bai ,  Nan Xu ,  Jinzhong Yao

IPC: H01L21/50 ,  H01L23/433 ,  H01L23/31 ,  H01L23/16 ,  H01L23/00 ,  H01L23/552 ,  H01L21/56

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/565 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/552 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method of assembling semiconductor devices includes placing an array of semiconductor dies on a die support. A cap array structure is provided that has a corresponding array of caps supported by a cap frame structure. The cap array structure and the array of semiconductor dies on the die support are aligned, with the caps extending over corresponding semiconductor dies, in a mold chase. The array of semiconductor dies and the array of caps are encapsulated with a molding compound in the mold chase. The encapsulated units of the semiconductor dies with the corresponding caps are removed from the mold chase and singulated. Singulating the encapsulated units may include removing the cap frame structure from the encapsulated units.

Abstract translation: 一种组装半导体器件的方法包括将半导体管芯的阵列放置在管芯支撑件上。 提供一种帽阵列结构，其具有由帽框架结构支撑的相应的帽阵列。 在模具追逐中，盖阵列结构和模具支撑件上的半导体管芯阵列与盖延伸在对应的半导体管芯上对齐。 半导体管芯阵列和盖阵列通过模具化合物封装在模具追逐中。 将具有相应盖的半导体管芯的封装单元从模具中取出并分离。 编码封装的单元可以包括从封装单元去除盖框架结构。