公开(公告)号：US20140147975A1

公开(公告)日：2014-05-29

申请号：US13689034

申请日：2012-11-29

Applicant: Burton J. Carpenter ,  Boon Yew Low ,  Shufeng Zhao

Inventor： Burton J. Carpenter ,  Boon Yew Low ,  Shufeng Zhao

IPC: H01L21/56

CPC classification number: H01L21/565 ,  H01L23/4334 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: Forming a packaged semiconductor device includes placing a semiconductor die attached to a carrier into a mold cavity having an injection port, wherein the semiconductor die has an encapsulant exclusion region on a top surface of the semiconductor die within an outer perimeter of the top surface; and flowing an encapsulant over the semiconductor die and carrier from the injection port, wherein the encapsulant flows around the encapsulant exclusion region to surround the encapsulant exclusion region without covering the encapsulant exclusion region. The encapsulant exclusion region has a first length corresponding to a single longest distance across the encapsulant exclusion region, wherein the first length is aligned, within 30 degrees, to a line defined by a shortest distance between an entry point of the injection port into the mold cavity and an outer perimeter of the encapsulant exclusion region.

Abstract translation: 形成封装的半导体器件包括将附接到载体的半导体管芯放置到具有注入端口的模具腔中，其中半导体管芯在顶表面的外周边内在半导体管芯的顶表面上具有密封排斥区域; 并且将密封剂从所述注入端口流过所述半导体管芯和载体，其中所述密封剂围绕所述密封剂排除区域流动以围绕所述密封剂排除区域而不覆盖所述密封剂排除区域。 密封剂排除区域具有对应于穿过密封剂排除区域的单个最长距离的第一长度，其中第一长度在30度内对准由注射端口进入模具的入口点之间的最短距离所限定的线 空腔和密封剂排除区域的外周边。

公开(公告)号：US20150118802A1

公开(公告)日：2015-04-30

申请号：US14464719

申请日：2014-08-21

Applicant: Boon Yew Low ,  Teck Beng Lau ,  Seng Kiong Teng ,  Shufeng Zhao

Inventor： Boon Yew Low ,  Teck Beng Lau ,  Seng Kiong Teng ,  Shufeng Zhao

IPC: B29C45/27 ,  B29C45/34 ,  H01L21/56 ,  B29C45/14

CPC classification number: H01L21/565 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A mold die includes a side wall forming a hollow cavity and opposing first and second axial ends. The side wall has first and second openings respectively at the first and second axial ends. Each of the first and second openings accesses the hollow cavity. A main wall is coupled to the side wall at the first end thereof and spans the first opening. A center of the main wall is aligned with a longitudinal axis of the side wall. The main wall defines a plane oriented generally perpendicularly with respect to the longitudinal axis of the side wall. First and second gates are formed through the main wall to access the hollow cavity. The first and second gates define a first line lying in the plane of the main wall. The center of the main wall is located on the first line between the first and second gates.

Abstract translation: 模具包括形成中空腔的侧壁和相对的第一和第二轴向端。 侧壁在第一和第二轴向端部分别具有第一和第二开口。 第一和第二开口中的每一个进入中空腔。 主壁在其第一端处联接到侧壁并跨越第一开口。 主壁的中心与侧壁的纵向轴线对准。 主壁限定了相对于侧壁的纵向轴线大致垂直定向的平面。 第一和第二门通过主壁形成以进入中空腔。 第一和第二门限定位于主墙平面中的第一行。 主墙的中心位于第一和第二门之间的第一条线上。

公开(公告)号：US20110248393A1

公开(公告)日：2011-10-13

申请号：US13021716

申请日：2011-02-05

Applicant: Yongsheng Lu ,  Bin Tian ,  Nan Xu ,  Jinzhong Yao ,  Shufeng Zhao

Inventor： Yongsheng Lu ,  Bin Tian ,  Nan Xu ,  Jinzhong Yao ,  Shufeng Zhao

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L23/3107 ,  H01L23/49548 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A lead frame for reducing detrimental effects of burr formation includes a lead frame that has leads where a portion of a top surface is removed from a first lead and a portion of a bottom surface is removed from a second lead adjacent to the first lead to reduce spacing between leads while reducing the detrimental effects of burr formation, such as shorting and the like, caused during singulation of a semiconductor device manufactured with the lead frame.

Abstract translation: 用于减少毛刺形成的有害影响的引线框架包括引线框架，其具有引线，其中顶表面的一部分从第一引线移除，并且底表面的一部分从邻近第一引线的第二引线移除以减少 导线之间的间隔，同时减少了由引线框制造的半导体器件的分割期间引起的毛刺形成的不利影响，例如短路等。

公开(公告)号：US08802508B2

公开(公告)日：2014-08-12

申请号：US13689034

申请日：2012-11-29

Applicant: Burton J. Carpenter ,  Boon Yew Low ,  Shufeng Zhao

Inventor： Burton J. Carpenter ,  Boon Yew Low ,  Shufeng Zhao

IPC: H01L21/82 ,  H01L21/56

CPC classification number: H01L21/565 ,  H01L23/4334 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: Forming a packaged semiconductor device includes placing a semiconductor die attached to a carrier into a mold cavity having an injection port, wherein the semiconductor die has an encapsulant exclusion region on a top surface of the semiconductor die within an outer perimeter of the top surface; and flowing an encapsulant over the semiconductor die and carrier from the injection port, wherein the encapsulant flows around the encapsulant exclusion region to surround the encapsulant exclusion region without covering the encapsulant exclusion region. The encapsulant exclusion region has a first length corresponding to a single longest distance across the encapsulant exclusion region, wherein the first length is aligned, within 30 degrees, to a line defined by a shortest distance between an entry point of the injection port into the mold cavity and an outer perimeter of the encapsulant exclusion region.

Abstract translation: 形成封装的半导体器件包括将附接到载体的半导体管芯放置到具有注入端口的模腔中，其中半导体管芯在顶表面的外周边内在半导体管芯的顶表面上具有封装排除区域; 并且将密封剂从所述注入端口流过所述半导体管芯和载体，其中所述密封剂围绕所述密封剂排除区域流动以围绕所述密封剂排除区域而不覆盖所述密封剂排除区域。 密封剂排除区域具有对应于穿过密封剂排除区域的单个最长距离的第一长度，其中第一长度在30度内对准由注射端口进入模具的入口点之间的最短距离所限定的线 空腔和密封剂排除区域的外周边。

公开(公告)号：US20110193207A1

公开(公告)日：2011-08-11

申请号：US13004031

申请日：2011-01-11

Applicant: Zhaojun Tian ,  Qingchun He ,  Qiang Liu ,  Jie Yang ,  Shufeng Zhao

Inventor： Zhaojun Tian ,  Qingchun He ,  Qiang Liu ,  Jie Yang ,  Shufeng Zhao

IPC: H01L23/495

CPC classification number: H01L23/49541 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A lead frame for providing electrical interconnection to a semiconductor die has a generally rectangular flag area having first and second major surfaces and four sides. The flag area is sized and shaped to receive a semiconductor die on one of the first and second major surfaces. A first row of leads is located adjacent to a first one of the four sides of the flag area and a second row of leads is located adjacent to a second one of the four sides of the flag area, where the second one of the four sides is adjacent to the first one of the four sides. The remaining two sides do not have any adjacent leads.

Abstract translation: 用于向半导体管芯提供电互连的引线框架具有大致矩形的标记区域，其具有第一和第二主表面和四个侧面。 标记区域的尺寸和形状被设计成在第一和第二主表面之一上接收半导体管芯。 第一排引线位于与标志区域的四个边中的第一个相邻的位置，并且第二排引线位于邻近标志区域的四个边的第二侧的位置，其中四个侧面中的第二个 毗邻四面的第一个。 剩下的两边没有任何相邻的导线。

公开(公告)号：US20130049180A1

公开(公告)日：2013-02-28

申请号：US13549517

申请日：2012-07-15

Applicant: Nan XU ,  Xingshou PANG ,  Bin TIAN ,  Shufeng ZHAO

Inventor： Nan XU ,  Xingshou PANG ,  Bin TIAN ,  Shufeng ZHAO

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L23/49541 ,  H01L21/4828 ,  H01L21/4842 ,  H01L23/3121 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A lead frame for a quad flat no-lead (QFN) type semiconductor device package includes a die pad, a plurality of leads that surround the die pad. The outer edge of leads includes a channel that extends from a lower surface to an upper surface of the leads. A semiconductor die is attached to the die pad. An inner edge of each lead is electrically connected to a corresponding bonding pad on the semiconductor die. The assembly is covered with an encapsulation material except that the outer edge of each lead and the corresponding channel are exposed. The channel allows solder to flow up the outer edge of a lead when the QFN device is soldered to a substrate, which improves the ability to perform visual inspection of the solder-lead connection.

Abstract translation: 用于四边形无引线（QFN）型半导体器件封装的引线框架包括管芯焊盘，围绕管芯焊盘的多个引线。 引线的外缘包括从引线的下表面延伸到上表面的通道。 半导体管芯附接到管芯焊盘。 每个引线的内边缘电连接到半导体管芯上相应的焊盘。 该组件被封装材料覆盖，除了每个引线的外边缘和相应的通道被暴露外。 当QFN器件焊接到衬底时，该通道允许焊料向上流过引线的外边缘，这提高了对焊锡引线连接进行目视检查的能力。

公开(公告)号：US08115288B2

公开(公告)日：2012-02-14

申请号：US13021716

申请日：2011-02-05

Applicant: Yongsheng Lu ,  Bin Tian ,  Nan Xu ,  Jinzhong Yao ,  Shufeng Zhao

Inventor： Yongsheng Lu ,  Bin Tian ,  Nan Xu ,  Jinzhong Yao ,  Shufeng Zhao

IPC: H01L21/60 ,  H01L23/495

CPC classification number: H01L23/3107 ,  H01L23/49548 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A lead frame for reducing detrimental effects of burr formation includes a lead frame that has leads where a portion of a top surface is removed from a first lead and a portion of a bottom surface is removed from a second lead adjacent to the first lead to reduce spacing between leads while reducing the detrimental effects of burr formation, such as shorting and the like, caused during singulation of a semiconductor device manufactured with the lead frame.

Abstract translation: 用于减少毛刺形成的有害影响的引线框架包括引线框架，其具有引线，其中顶表面的一部分从第一引线移除，并且底表面的一部分从邻近第一引线的第二引线移除以减少 导线之间的间隔，同时减少了由引线框制造的半导体器件的分割期间引起的毛刺形成的不利影响，例如短路等。