公开(公告)号：US08635581B1

公开(公告)日：2014-01-21

申请号：US13842502

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Chen W. Tseng ,  Weiguang Lu ,  Karthy Rajasekharan ,  Matthew H. Klein ,  Restu I. Ismail

IPC: G06F11/22 ,  G06F17/50

CPC classification number: G06F11/263 ,  G06F2217/14

Abstract: A method, non-transitory computer readable medium, and apparatus for performing single event upset detection and correction are disclosed. For example, the method comprises: setting, by a processor, at least one starting address for each of a plurality of rows of a design for an integrated circuit, setting, by the processor, at least one ending address for each of the plurality of rows of the design, and performing, by the processor, the single event upset detection and correction scan in parallel, from the at least one starting address for each of the plurality of rows to the at least one ending address for each of the plurality of rows.

Abstract translation: 公开了一种用于执行单事件不正常检测和校正的方法，非暂时性计算机可读介质和装置。 例如，该方法包括：由处理器设置用于集成电路的设计的多行中的每一行的至少一个起始地址，由处理器设置用于多个集合电路中的每一个的至少一个结束地址 并且由处理器并行执行单个事件镦锻检测和校正扫描，从多个行中的每个行的至少一个起始地址到多个行中的每一个的至少一个结束地址 行。

公开(公告)号：US12148464B2

公开(公告)日：2024-11-19

申请号：US17385313

申请日：2021-07-26

Applicant: Xilinx, Inc.

Inventor： Michael Tsivyan ,  Shidong Zhou ,  Karthy Rajasekharan ,  Weiguang Lu ,  Jing Jing Chen ,  Mehul Vashi

IPC: G11C11/419 ,  G11C11/418 ,  H10B10/00

Abstract: First and second sensing circuits are coupled to first and second data lines, respectively, and sense levels of current leakage or a memory cell state on the first and second data lines. First and second keeper circuits are coupled to the first and second data lines, respectively, and drive the first and second data lines by a voltage supply through biased transistors. First and second leakage latches are coupled to receive and latch state of signals output from the first and second sensing circuits, respectively. A control circuit is coupled to the first leakage latch, second leakage latch, and outputs of the first and second sensing circuits. The control circuit is configured to select either the signal output from the first sensing circuit or the signal output from the second sensing circuit in response to states of the first and second leakage latches.

公开(公告)号：US10108376B1

公开(公告)日：2018-10-23

申请号：US15587294

申请日：2017-05-04

Applicant: Xilinx, Inc.

Inventor： Michelle E. Zeng ,  Subodh Kumar ,  Uma Durairajan ,  Weiguang Lu ,  Hsiao H. Chen

IPC: G11C16/04 ,  G06F3/06 ,  G06F11/10

Abstract: Circuits and methods for initializing a memory. Each row of the memory includes data bits and associated parity bits. A write buffer contains bit values for initializing the memory, and a control circuit performs a first set of write operations that write values from the write buffer to the data bits of the memory without writing values to the associated parity bits. The write buffer performs a second set of write operations that write values from the write buffer to the parity bits associated with the data bits without writing data to the data bits.

公开(公告)号：US10763862B1

公开(公告)日：2020-09-01

申请号：US16285588

申请日：2019-02-26

Applicant: Xilinx, Inc.

Inventor： Rafael C. Camarota ,  Ui S. Han ,  Weiguang Lu

IPC: H03K19/17736 ,  G06F30/33

Abstract: Examples described herein provide for a boundary logic interface (BLI) to a programmable logic region in an integrated circuit (IC), and methods for operating such IC. An example IC includes a programmable logic region and boundary logic interfaces. The programmable logic region includes columns of interconnect elements disposed between columns of logic elements. The boundary logic interfaces are at respective ends of and communicatively connected to the columns of interconnect elements. The boundary logic interfaces are outside of a boundary of the programmable logic region. A first boundary logic interface (BLI) of the boundary logic interfaces is configured to be communicatively connected to an exterior circuit. The first BLI includes an interface configured to communicate a signal between the exterior circuit and the programmable logic region.

公开(公告)号：US08922242B1

公开(公告)日：2014-12-30

申请号：US14185587

申请日：2014-02-20

Applicant: Xilinx, Inc.

Inventor： Chen W. Tseng ,  Weiguang Lu ,  Karthy Rajasekharan

IPC: H03K19/007 ,  H03K19/177

CPC classification number: H03K19/17764 ,  H03K19/17768

Abstract: Methods and circuits are disclosed for backing up the value of a bi-stable circuit included in a set of programmable logic circuits of a programmable IC. The programmable logic circuits are configured to implement logic circuits having functions based on data values stored in a used portion of a plurality of configuration memory cells. The programmable IC includes a backup control circuit configured to back up and restore the value of the bi-stable circuit. In response to a first signal, a first data value stored by the bi-stable circuit is retrieved and stored in a first one of the plurality of configuration memory cells that is unused in implementing the logic circuits. In response to a second signal, the first data value is retrieved from the first one of the plurality of configuration memory cells and stored in the bi-stable circuit.

Abstract translation: 公开了用于备份可编程IC的一组可编程逻辑电路中包括的双稳态电路的值的方法和电路。 可编程逻辑电路被配置为实现具有基于存储在多个配置存储器单元的使用部分中的数据值的功能的逻辑电路。 可编程IC包括配置为备份和恢复双稳电路的值的备用控制电路。 响应于第一信号，由双稳电路存储的第一数据值被检索并存储在多个配置存储器单元中的第一个未被用于实现逻辑电路的配置存储器单元中。 响应于第二信号，第一数据值从多个配置存储器单元中的第一个被检索并存储在双稳态电路中。

公开(公告)号：US10963170B2

公开(公告)日：2021-03-30

申请号：US16262420

申请日：2019-01-30

Applicant: Xilinx, Inc.

Inventor： Subodh Kumar ,  David P. Schultz ,  Weiguang Lu ,  Michelle Zeng

IPC: G06F3/06

Abstract: Embodiments herein describe a reconfigurable integrated circuit (IC) where data can be retained in memory when performing a partial reconfiguration. Partial reconfiguration includes reconfiguring programmable logic in the IC while certain functions of the IC remain operational or active. In one embodiment, the reconfigurable IC includes control logic for saving or retaining data in the IC during a partial reconfiguration. That is, rather than clearing the memory elements, the user can specify that the memory blocks containing certain data should be retained while the other memory blocks can be cleared. In this manner, the data can be retained in the IC during a partial reconfiguration which saves time, power, and cost. Once partial reconfiguration is complete, the newly configured programmable logic can retrieve and process the saved data from the on-chip memory.

公开(公告)号：US10169264B1

公开(公告)日：2019-01-01

申请号：US15639752

申请日：2017-06-30

Applicant: Xilinx, Inc.

Inventor： Michelle E. Zeng ,  Subodh Kumar ,  Uma Durairajan ,  Weiguang Lu ,  Karthy Rajasekharan ,  Kumar Rahul

IPC: G06F13/16 ,  H03K19/177 ,  G06F3/06 ,  G06F13/40 ,  G11C7/10 ,  G01R31/3185

Abstract: In an example, a memory circuit in a programmable integrated circuit (IC) includes: a control port and a clock port; a configurable random access memory (RAM) having a control input and a clock input; input multiplexer logic coupled to the control input and the clock input; and a state machine coupled to the input multiplexer logic and configuration logic of the programmable IC, the state machine configured to: in response to being enabled by the configuration logic, control the input multiplexer logic to switch a connection of the control input from the control port to the state machine and, subsequently, switch a connection of the clock input from the clock port to a configuration clock source; and in response to being disabled by the configuration logic, control the input multiplexer logic to switch the connection of the clock input from the configuration clock source to the clock port and, subsequently, switch the connection of the control input from the state machine to the control port.

公开(公告)号：US09722613B1

公开(公告)日：2017-08-01

申请号：US14867461

申请日：2015-09-28

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  Weiguang Lu ,  Paige A. Kolze

IPC: H03K19/177

CPC classification number: H03K19/17756 ,  H03K19/17728 ,  H03K19/1774

Abstract: A circuit arrangement for enabling a partial reconfiguration of a circuit implemented in an integrated circuit device is described. The circuit arrangement comprises a plurality of circuit blocks, wherein each circuit block is configurable to implement a predetermined function and comprises a control circuit configured to receive a global enable signal and a plurality of global reconfiguration signals; and a routing network coupled to the plurality of circuit blocks for routing the global enable signal and the plurality of global reconfiguration signals to each circuit block of the plurality of circuit blocks; wherein each circuit block of the plurality of circuit blocks is configured to independently receive a local enable signal enabling a partial reconfiguration of the circuit in response to the plurality of global reconfiguration signals.

公开(公告)号：US20230023614A1

公开(公告)日：2023-01-26

申请号：US17385313

申请日：2021-07-26

Applicant: Xilinx, Inc.

Inventor： Michael Tsivyan ,  Shidong Zhou ,  Karthy Rajasekharan ,  Weiguang Lu ,  Jing Jing Chen ,  Mehul Vashi

IPC: G11C11/419 ,  G11C11/418 ,  H01L27/11

Abstract: First and second sensing circuits are coupled to first and second data lines, respectively, and sense levels of current leakage or a memory cell state on the first and second data lines. First and second keeper circuits are coupled to the first and second data lines, respectively, and drive the first and second data lines by a voltage supply through biased transistors. First and second leakage latches are coupled to receive and latch state of signals output from the first and second sensing circuits, respectively. A control circuit is coupled to the first leakage latch, second leakage latch, and outputs of the first and second sensing circuits. The control circuit is configured to select either the signal output from the first sensing circuit or the signal output from the second sensing circuit in response to states of the first and second leakage latches.

公开(公告)号：US11386009B2

公开(公告)日：2022-07-12

申请号：US16670570

申请日：2019-10-31

Applicant: XILINX, INC.

Inventor： David P. Schultz ,  Weiguang Lu ,  Karthy Rajasekharan ,  Shidong Zhou ,  Michael Tsivyan ,  Jing Jing Chen ,  Sourabh Goyal

IPC: G06F12/0855 ,  G06F9/30 ,  G06F12/06 ,  G06F12/0895 ,  G06F13/16

Abstract: An example configuration system for a programmable device includes: a configuration memory read/write unit configured to receive configuration data for storage in a configuration memory of the programmable device, the configuration memory comprising a plurality of frames; a plurality of configuration memory read/write controllers coupled to the configuration memory read/write unit; a plurality of fabric sub-regions (FSRs) respectively coupled to the plurality of configuration memory read/write controllers, each FSR including a pipeline of memory cells of the configuration memory disposed between buffers and a configuration memory read/write pipeline unit coupled between the pipeline and a next one of the plurality of FSRs.