公开(公告)号：US09208043B1

公开(公告)日：2015-12-08

申请号：US13842140

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Chen W. Tseng ,  Restu I. Ismail ,  Robert Le

IPC: G06F11/00 ,  G06F11/263

CPC classification number: G06F11/263 ,  G01R31/31816 ,  G01R31/318342

Abstract: A method, non-transitory computer readable medium, and apparatus for performing fault injection and verification on an integrated circuit are disclosed. For example, the method generates a mask file for one or more modules of a hierarchical design, wherein the mask file identifies one or more essential bits, receives a selection of one of the one or more modules as a selected module for the fault injection and the verification to be applied, performs the fault injection on at least one essential bit of the selected module based upon the mask file for the selected module, and performs the verification on the selected module.

Abstract translation: 公开了一种在集成电路上执行故障注入和验证的方法，非暂时计算机可读介质和装置。 例如，该方法为分层设计的一个或多个模块生成掩模文件，其中掩模文件识别一个或多个必要位，接收作为用于故障注入的所选模块的一个或多个模块之一的选择， 要应用的验证，基于所选模块的掩模文件对所选模块的至少一个基本位执行故障注入，并对所选模块执行验证。

公开(公告)号：US08635581B1

公开(公告)日：2014-01-21

申请号：US13842502

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Chen W. Tseng ,  Weiguang Lu ,  Karthy Rajasekharan ,  Matthew H. Klein ,  Restu I. Ismail

IPC: G06F11/22 ,  G06F17/50

CPC classification number: G06F11/263 ,  G06F2217/14

Abstract: A method, non-transitory computer readable medium, and apparatus for performing single event upset detection and correction are disclosed. For example, the method comprises: setting, by a processor, at least one starting address for each of a plurality of rows of a design for an integrated circuit, setting, by the processor, at least one ending address for each of the plurality of rows of the design, and performing, by the processor, the single event upset detection and correction scan in parallel, from the at least one starting address for each of the plurality of rows to the at least one ending address for each of the plurality of rows.

Abstract translation: 公开了一种用于执行单事件不正常检测和校正的方法，非暂时性计算机可读介质和装置。 例如，该方法包括：由处理器设置用于集成电路的设计的多行中的每一行的至少一个起始地址，由处理器设置用于多个集合电路中的每一个的至少一个结束地址 并且由处理器并行执行单个事件镦锻检测和校正扫描，从多个行中的每个行的至少一个起始地址到多个行中的每一个的至少一个结束地址 行。