公开(公告)号：US10169264B1

公开(公告)日：2019-01-01

申请号：US15639752

申请日：2017-06-30

Applicant: Xilinx, Inc.

Inventor： Michelle E. Zeng ,  Subodh Kumar ,  Uma Durairajan ,  Weiguang Lu ,  Karthy Rajasekharan ,  Kumar Rahul

IPC: G06F13/16 ,  H03K19/177 ,  G06F3/06 ,  G06F13/40 ,  G11C7/10 ,  G01R31/3185

Abstract: In an example, a memory circuit in a programmable integrated circuit (IC) includes: a control port and a clock port; a configurable random access memory (RAM) having a control input and a clock input; input multiplexer logic coupled to the control input and the clock input; and a state machine coupled to the input multiplexer logic and configuration logic of the programmable IC, the state machine configured to: in response to being enabled by the configuration logic, control the input multiplexer logic to switch a connection of the control input from the control port to the state machine and, subsequently, switch a connection of the clock input from the clock port to a configuration clock source; and in response to being disabled by the configuration logic, control the input multiplexer logic to switch the connection of the clock input from the configuration clock source to the clock port and, subsequently, switch the connection of the control input from the state machine to the control port.

公开(公告)号：US08635581B1

公开(公告)日：2014-01-21

申请号：US13842502

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Chen W. Tseng ,  Weiguang Lu ,  Karthy Rajasekharan ,  Matthew H. Klein ,  Restu I. Ismail

IPC: G06F11/22 ,  G06F17/50

CPC classification number: G06F11/263 ,  G06F2217/14

Abstract: A method, non-transitory computer readable medium, and apparatus for performing single event upset detection and correction are disclosed. For example, the method comprises: setting, by a processor, at least one starting address for each of a plurality of rows of a design for an integrated circuit, setting, by the processor, at least one ending address for each of the plurality of rows of the design, and performing, by the processor, the single event upset detection and correction scan in parallel, from the at least one starting address for each of the plurality of rows to the at least one ending address for each of the plurality of rows.

Abstract translation: 公开了一种用于执行单事件不正常检测和校正的方法，非暂时性计算机可读介质和装置。 例如，该方法包括：由处理器设置用于集成电路的设计的多行中的每一行的至少一个起始地址，由处理器设置用于多个集合电路中的每一个的至少一个结束地址 并且由处理器并行执行单个事件镦锻检测和校正扫描，从多个行中的每个行的至少一个起始地址到多个行中的每一个的至少一个结束地址 行。

公开(公告)号：US08922242B1

公开(公告)日：2014-12-30

申请号：US14185587

申请日：2014-02-20

Applicant: Xilinx, Inc.

Inventor： Chen W. Tseng ,  Weiguang Lu ,  Karthy Rajasekharan

IPC: H03K19/007 ,  H03K19/177

CPC classification number: H03K19/17764 ,  H03K19/17768

Abstract: Methods and circuits are disclosed for backing up the value of a bi-stable circuit included in a set of programmable logic circuits of a programmable IC. The programmable logic circuits are configured to implement logic circuits having functions based on data values stored in a used portion of a plurality of configuration memory cells. The programmable IC includes a backup control circuit configured to back up and restore the value of the bi-stable circuit. In response to a first signal, a first data value stored by the bi-stable circuit is retrieved and stored in a first one of the plurality of configuration memory cells that is unused in implementing the logic circuits. In response to a second signal, the first data value is retrieved from the first one of the plurality of configuration memory cells and stored in the bi-stable circuit.

Abstract translation: 公开了用于备份可编程IC的一组可编程逻辑电路中包括的双稳态电路的值的方法和电路。 可编程逻辑电路被配置为实现具有基于存储在多个配置存储器单元的使用部分中的数据值的功能的逻辑电路。 可编程IC包括配置为备份和恢复双稳电路的值的备用控制电路。 响应于第一信号，由双稳电路存储的第一数据值被检索并存储在多个配置存储器单元中的第一个未被用于实现逻辑电路的配置存储器单元中。 响应于第二信号，第一数据值从多个配置存储器单元中的第一个被检索并存储在双稳态电路中。

公开(公告)号：US12148464B2

公开(公告)日：2024-11-19

申请号：US17385313

申请日：2021-07-26

Applicant: Xilinx, Inc.

Inventor： Michael Tsivyan ,  Shidong Zhou ,  Karthy Rajasekharan ,  Weiguang Lu ,  Jing Jing Chen ,  Mehul Vashi

IPC: G11C11/419 ,  G11C11/418 ,  H10B10/00

Abstract: First and second sensing circuits are coupled to first and second data lines, respectively, and sense levels of current leakage or a memory cell state on the first and second data lines. First and second keeper circuits are coupled to the first and second data lines, respectively, and drive the first and second data lines by a voltage supply through biased transistors. First and second leakage latches are coupled to receive and latch state of signals output from the first and second sensing circuits, respectively. A control circuit is coupled to the first leakage latch, second leakage latch, and outputs of the first and second sensing circuits. The control circuit is configured to select either the signal output from the first sensing circuit or the signal output from the second sensing circuit in response to states of the first and second leakage latches.

公开(公告)号：US20230023614A1

公开(公告)日：2023-01-26

申请号：US17385313

申请日：2021-07-26

Applicant: Xilinx, Inc.

Inventor： Michael Tsivyan ,  Shidong Zhou ,  Karthy Rajasekharan ,  Weiguang Lu ,  Jing Jing Chen ,  Mehul Vashi

IPC: G11C11/419 ,  G11C11/418 ,  H01L27/11

Abstract: First and second sensing circuits are coupled to first and second data lines, respectively, and sense levels of current leakage or a memory cell state on the first and second data lines. First and second keeper circuits are coupled to the first and second data lines, respectively, and drive the first and second data lines by a voltage supply through biased transistors. First and second leakage latches are coupled to receive and latch state of signals output from the first and second sensing circuits, respectively. A control circuit is coupled to the first leakage latch, second leakage latch, and outputs of the first and second sensing circuits. The control circuit is configured to select either the signal output from the first sensing circuit or the signal output from the second sensing circuit in response to states of the first and second leakage latches.

公开(公告)号：US11386009B2

公开(公告)日：2022-07-12

申请号：US16670570

申请日：2019-10-31

Applicant: XILINX, INC.

Inventor： David P. Schultz ,  Weiguang Lu ,  Karthy Rajasekharan ,  Shidong Zhou ,  Michael Tsivyan ,  Jing Jing Chen ,  Sourabh Goyal

IPC: G06F12/0855 ,  G06F9/30 ,  G06F12/06 ,  G06F12/0895 ,  G06F13/16

Abstract: An example configuration system for a programmable device includes: a configuration memory read/write unit configured to receive configuration data for storage in a configuration memory of the programmable device, the configuration memory comprising a plurality of frames; a plurality of configuration memory read/write controllers coupled to the configuration memory read/write unit; a plurality of fabric sub-regions (FSRs) respectively coupled to the plurality of configuration memory read/write controllers, each FSR including a pipeline of memory cells of the configuration memory disposed between buffers and a configuration memory read/write pipeline unit coupled between the pipeline and a next one of the plurality of FSRs.

公开(公告)号：US10825541B1

公开(公告)日：2020-11-03

申请号：US16150064

申请日：2018-10-02

Applicant: Xilinx, Inc.

Inventor： Henry Fu ,  Weiguang Lu ,  Karthy Rajasekharan

IPC: G11C29/10 ,  G11C29/36 ,  G11C29/38

Abstract: Examples herein describe a self-test process where an integrated circuit includes a test controller responsible for testing a plurality of frames in the memory of an integrated circuit. The test controller can receive a test pattern which the controller duplicates and stores in each of the plurality of frames. However, frames may be non-uniform meaning the frames have varying sizes. As such, some of the frames may only store parts of the test pattern rather than all of it. In any case, the test controller reads out the stored data and generates a checksum which can then be compared to a baseline checksum generated from simulating the integrated circuit using design code to determine whether there is a manufacturing defect in the frames.

公开(公告)号：US10666266B1

公开(公告)日：2020-05-26

申请号：US16212566

申请日：2018-12-06

Applicant: Xilinx, Inc.

Inventor： Karthy Rajasekharan ,  Weiguang Lu

IPC: H03K19/1776 ,  H03K19/17724 ,  H03K19/17704

Abstract: Apparatus and method relate generally to a configuration engine. In one such configuration engine for a programmable circuit, a frame counter includes a cascade of frame incrementer circuits associated with columns for a row of circuit blocks. Each frame incrementer circuit is configured to provide frame sums for frames associated with the circuit blocks. The frame counter is configured to sequentially add the frame sums for the columns to provide corresponding frame totals respectively for circuit types of the circuit blocks. A termination circuit is configured to multiplex the frame totals onto a data bus. A row controller is configured to initiate the frame counter and to selectively access the frame totals provided to the data bus.